AC’97 Controller Unit

Figure 13-9. PCM Transmit and Receive Operation

Transmit Data

TxEntry15

PCM Transmit FIFO

TxEntry3

TxEntry2

TxEntry1

 

TxEntry0

Right

Left

31

16 15

Processor/DMA Write

 

 

 

Receive Data

 

Processor/DMA

 

 

 

 

 

 

 

 

 

 

Read

 

 

 

 

 

 

 

 

 

 

 

RxEntry15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCDR Register

 

PCM Receive FIFO

 

 

 

 

 

 

 

 

 

31

 

0

 

 

 

 

 

 

 

 

RxFIFO

 

 

 

 

 

TxFIFO

 

RxEntry3

 

 

Written

Read

 

 

 

 

 

 

 

 

 

RxEntry2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RxEntry1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RxEntry0

 

 

 

 

 

 

 

Right

 

Left

0

0

 

 

 

 

 

31

16 15

13.8.3.9Mic-In Control Register (MCCR)

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 13-15. MCCR Bit Definitions

Physical Address

MCCR Register

AC’97 Controller Unit

4050_0008

 

 

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4

reserved

3

2

1

0

FEIE

 

reserved

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

Bits

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31:4

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO Error Interrupt Enable (FEIE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit controls whether the occurrence of a receive FIFO error will cause an interrupt or

 

 

 

 

3

 

 

FEIE

 

not.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = No interrupt will occur even if bit 4 in the MCSR is set

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 = An interrupt will occur if bit 4 in the MCSR is set.

 

 

 

 

 

 

 

 

 

 

 

 

2:0

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13.8.3.10Mic-In Status Register (MCSR)

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Intel® PXA255 Processor Developer’s Manual

13-27

Page 479
Image 479
Intel PXA255 Mic-In Control Register Mccr, Mic-In Status Register Mcsr, Mccr Bit Definitions, Mccr Register, 40500008