Intel PXA255 manual Slow Infrared Asynchronous Interface, Trailing Bytes in the Receive Fifo

UARTs

Note: Ensure that the DMAC has finished previous receive DMA requests before the error interrupt handler begins to clear the errors from the FIFO.

10.4.5.1Trailing Bytes in the Receive FIFO

Trailing bytes occur when the number of entries in the receive FIFO is less than its trigger level and no more data is being received. In such a case, a receive DMA request is not generated. To read the trailing bytes follow these steps:

1.Wait for a character timeout indication interrupt. The character timeout indication interrupt must be enabled.

2.Disable the receive DMA channel and wait for it to stop.

3.Read one byte at a time. The FIFO is empty when LSR[DR] is cleared.

4.Re-enable the receive DMA channel.

10.4.6Slow Infrared Asynchronous Interface

The Slow Infrared (SIR) interface is used with the STUART to support two-way wireless communication that uses infrared transmission. The SIR provides a transmit encoder and receive decoder to support a physical link that conforms to the IRDA Serial Infrared Specification Version 1.1.

The SIR interface does not contain the actual IR LED driver or the receiver amplifier. The I/O pins attached to the SIR only have digital CMOS level signals. The SIR supports two-way communication, but full duplex communication is not possible because reflections from the transmit LED enter the receiver. The SIR interface supports frequencies up to 115.2 kbps. Because the input clock is 14.7456 MHz, the baud divisor must be eight or more.

10.4.6.1Infrared Selection Register (ISR)

The IRDA module is managed through the UART to which it is attached. The ISR, shown in Table 10-17, controls IRDA functions.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Intel® PXA255 Processor Developer’s Manual 10-23