Memory Controller

Table 6-25provides a comparison of supported Asynchronous Static Memory types.

Table 6-25. Asynchronous Static Memory and Variable Latency I/O Capabilities

 

 

 

 

Timing (Memory Clocks)

 

 

 

 

 

 

 

 

 

 

 

MSCx[RTx]

Device

Burst

 

 

Burst

Burst

 

Burst

Type

Read

nOE

 

Write

nWE

nWE

 

 

nOE

 

 

Address

Assert

 

Address

Assert

De-

 

 

 

Deassert

 

 

Assert

 

 

Assert

 

assert

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Non-burst

 

 

 

 

 

 

 

000

ROM or

RDF+1

RDF+1

 

0

N/A

RDF+1

N/A

 

Flash

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

001

SRAM

RDF+1

RDF+1

 

0

RDN+2

RDN+1

1

 

 

 

 

 

 

 

 

 

 

Burst-of-4

RDF+1

RDF+1

 

 

 

 

 

010

ROM or

(0,4)

(0,4)

 

0

N/A

RDF+1

N/A

Flash (non-

RDN+1

RDN+1

 

 

 

 

 

 

 

 

burst writes)

(1:3,5:7)

(1:3,5:7)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Burst-of-8

RDF+1

RDF+1

 

 

 

 

 

 

ROM or

 

 

 

 

 

 

(0)

(0)

 

 

 

 

 

011

Flash

 

0

N/A

RDF+1

N/A

RDN+1

RDN+1

 

 

(non-burst

 

 

 

 

 

 

(1:7)

(1:7)

 

 

 

 

 

 

writes)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

100

Variable

RDF+

RDF+1+

 

RDN+2

RDF+

RDF+1+

RDN+2

Latency I/O

RDN+2+waits

waits

 

RDN+2+waits

waits

 

 

 

 

 

 

 

 

 

 

 

 

 

6.7.4ROM Interface

The processor provides programmable timing for both burst and non-burst ROMs. The RDF field in MSCx is the latency (in memory clock cycles) for the first, and all subsequent, data beats from non-burst ROMs, and the first data beat from a burst ROM. RDN is the latency for the burst data beats after the first for burst ROMs. RRR delays the following access to a different memory space to allow time for the current ROM to three-state the data bus.

RRR must be programmed with the maximum tOFF value, as specified by the ROM manufacturer.

For hardware reset initialization values, refer to Section 6.8. MSC0[15:0] is selected when the address space corresponding to nCS0 is accessed. The processor supports a ROM burst size of 1, 4, or 8 by configuring the MSCx[RTx] register bits to 0, 2 or 3 respectfully.

6-50

Intel® PXA255 Processor Developer’s Manual

Page 232
Image 232
Intel PXA255 manual ROM Interface, Timing Memory Clocks MSCxRTx Device, Nwe Noe, Assert