I2C Bus Interface Unit

9.6.3Read 1 Byte as a Master

1.Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read.

2.Initiate the write.

Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]

3.When an IDBR Transmit Empty interrupt occurs.

Read ISR: IDBR Transmit Empty (1), Unit busy (1), R/nW bit (1)

4.Write a 1 to the ISR[ITE] bit to clear the interrupt.

5.Initiate the read.

Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[ACKNAK], set ICR[TB]

6.When an IDBR Receive full interrupt occurs (unit is sending STOP).

Read ISR: IDBR Receive Full (1), Unit Busy (x), R/nW bit (1), ACK/NAK bit (1)

7.Write a 1 to the ISR[IRF] bit to clear the interrupt.

8.Read IDBR data.

9.Clear ICR[STOP] and ICR[ACKNAK] bits

9.6.4Write 2 Bytes and Repeated Start Read 1 Byte as a Master

1.Load target slave address and R/nW bit in the IDBR. R/nW must be 0 for a write.

2.Initiate the write.

Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]

3.When an IDBR Transmit Empty interrupt occurs.

Read ISR: IDBR Transmit Empty (1), Unit Busy (1), R/nW bit (0)

4.Write a 1 to the ISR[ITE] bit to clear interrupt.

5.Load data byte to be transferred in the IDBR.

6.Initiate the write.

Clear ICR[START], clear ICR[STOP], set ICR[ALDIE], set ICR[TB]

7.When an IDBR Transmit Empty interrupt occurs.

Read ISR: IDBR Transmit Empty (1), Unit busy (1), R/nW bit (0)

8.Write a 1 to the ISR[ITE] bit to clear interrupt.

9.Repeat steps 5-8 one time.

10.Load target slave address and R/nW bit in the IDBR. R/nW must be 1 for a read.

11.Send repeated start as a master.

Set ICR[START], clear ICR[STOP], clear ICR[ALDIE], set ICR[TB]

12.When an IDBR Transmit Empty interrupt occurs.

Read ISR: IDBR Transmit Empty (1), Unit busy (1), R/nW bit (1)

13.Write a 1 to the ISR[ITE] bit to clear interrupt.

14.Initiate the read.

Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[ACKNAK], set ICR[TB]

15.When an IDBR Receive full interrupt occurs (unit is sending stop).

Read ISR: IDBR Receive Full (1), Unit Busy (x), R/nW bit (1), ACK/NAK bit (1)

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Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual Write 2 Bytes and Repeated Start Read 1 Byte as a Master