Memory Controller

Table 6-29. Card Interface Command Assertion Code Table

MCMEMx_ASST

 

 

x_ASST_HOLD

x_ASST_WAIT +

 

 

x_ASST_HOLD

MCATTx_ASST

x_ASST_WAIT

 

 

 

 

 

 

MCIOx_ASST

 

 

 

 

 

 

 

 

(nPIOW asserted)

(nPIOR asserted)

(nPIOW asserted)

(nPIOR asserted)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

# MEMCLKs

# MEMCLKs

# MEMCLKs

# MEMCLKs

# MEMCLKs

 

 

(minimum)

(minimum)

 

Code

(minimum)

Programmed

to assert

to assert

(minimum)

(minimum)

decimal

to wait before

Bit Value

value

checking for

command

command

command

command

 

(nPIOW) after

(nPIOR) after

assertion time

assertion time

 

 

nPWAIT=’1’

 

 

nPWAIT=’1’

nPWAIT=’1’

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Code)

(Code)

(Code + 2)

(2*Code + 3)

(2*Code + 4)

(3*Code + 5)

(3*Code + 6)

 

 

 

 

 

 

 

 

11101

29

31

 

61

62

92

93

 

 

 

 

 

 

 

 

11110

30

32

 

63

64

95

96

 

 

 

 

 

 

 

 

11111

31

33

 

65

66

98

99

 

 

 

 

 

 

 

 

6.8.2Expansion Memory Configuration Register (MECR)

To eliminate external hardware, the two bits in MECR, shown in Table 6-30, are used to signal the memory controller when a card (16-Bit PC Card/Compact Flash) is inserted in the socket and the number of cards supported in the system. The number-of-sockets bit is required because the PSKTSEL pin is used as the nOE for the data transceivers in single socket mode. The card-is-there bit is used to reduce external hardware by ignoring nIOIS16 and nPWAIT when there is no card inserted in the socket.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 6-30. MECR Bit Definition

4800_0014

MECR

Memory Controller

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 0

CIT NOS

0 0

Bits

Name

 

Description

 

 

 

31:2

reserved

 

 

 

 

 

Card-Is-There

 

 

0 –

No card inserted

1

CIT

1 –

Card inserted

Must be set by software when at least one card is present and must be cleared when all cards are removed.

 

 

Number-of-Sockets

0

NOS

0 –

1

Socket

 

 

1 –

2

Sockets

Intel® PXA255 Processor Developer’s Manual

6-63

Page 245
Image 245
Intel PXA255 manual Expansion Memory Configuration Register Mecr, Mecr Bit Definition, Cit Nos