USB Device Controller

12.4.2Bus-Powered Devices

The processor does not support bus-powered devices because it is required to consume less that 500 µA when the host issues a suspend (see Section 7.2.3 of the USB Specification, version 1.1). The processor cannot limit the amount of current it consumes to 500 µA unless it enters sleep mode. When processor enters sleep mode it resets the USB registers and does not respond to its host-assigned address.

12.5UDC Operation

When a USB interrupt is received, software is directed to the USB ISR. USIR is level sensitive. Be sure to clear USIR as the last step before exiting the ISR. Upon exiting the ISR, the user should always clear the interrupt source bit, then clear the USIR. On power up or after a reset, software initially enables only EP0 interrupt. The other interrupts are enabled as required by the SET_CONFIG command.

12.5.1Case 1: EP0 Control Read

1.When software starts, it initializes a software state machine to EP0_IDLE. The software state machine is used to track endpoints stages when software communicates with the host PC.

2.The host PC sends a SETUP command.

3.UDC generates an EP0 Interrupt.

4.Software determines that the UDCCS0[SA] and UDCCS0[OPR] bits are set. This indicates that a new OUT packet is in the EP0 Buffer and identifies a SETUP transaction.

5.Software reads the data into a buffer while UDCCS0[RNE] bit (receiver not empty) is set.

6.Software parses the command in the buffer and determines that it is a Control Read.

7.Software starts to load the UDDR0 register FIFO with the first data packet and sets the internal state machine to EP0_IN_DATA_PHASE.

8.After it reads and parses the data, software clears the UDCCS0[SA] and the UDCCS0[OPR] bits and sets the UDCCS0[IPR] bit, if transmitting less than MAX_PACKET bytes, which prompts the UDC to transmit the data on the next IN. The UDC sends NAKs to all requests on this EP until the UDCCS0[IPR] bit is set.

9.Software clears the UDC interrupt bit and returns from the interrupt service routine.

10.The host PC issues an IN packet, which the UDC sends data back to the host. After the host PC sends an ACK to the UDC, the UDC clears the UDDCS0[IPR] bit and generates an interrupt.

11.Software enters the ISR routine and examines its internal state machine. It determines that it is in the EP0_IN_DATA_PHASE state and must transmit more data. Software loads the next amount of data, sets the UDCCS0[IPR] bit if necessary, and returns from the interrupt. The internal state machine is not affected.

12.Repeat Steps 10 and 11 until all the data is transmitted or the last data packet is a short packet.

13.If the last packet software sends is a short packet, it sets its internal state machine to EP0_END_XFER. If the last data packet ends on a 16-byte boundary, software sets UDCCS0[IPR] to send a zero-length packet without loading data in the FIFO. After it sends the zero-length packet, software sets the internal state machine to EP0_END_XFER.

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Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual UDC Operation, Bus-Powered Devices, Case 1 EP0 Control Read