Memory Controller

6.7.4.1ROM Timing Diagrams and Parameters

Figure 6-17, Figure 6-18, and Figure 6-19show the timings for burst and non-burst ROMs.

Figure 6-17. 32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0[RDF] = 4, MSC0[RDN] = 1, MSC0[RRR] = 1)

0ns

50ns

 

100ns

 

 

150ns

 

CLK_MEM

 

 

 

 

 

 

 

nCS[0]

 

 

 

 

 

 

 

 

tAS

 

 

 

 

 

 

MA[25:5]

 

 

 

 

 

 

 

 

RDF+2

 

RDN+1

 

 

 

 

MA[4:2]

0

1

2

3

4

5

6

MA[1:0]

 

 

 

"00"

 

 

 

 

RDF+1

 

 

 

 

 

 

nADV(nSDCAS)

tCES

nOE nWE RDnWR

tDOH

tDSOH

MD[31:0]

200ns

250ns

 

 

 

 

 

 

 

7

RRR*2+1

tCEH

DQM[3:0] nCS[1]

* MSC0:RDF0 = 4, RDN0 = 1, RRR0 = 1

"0000"

tAS = Address Setup to nCS asserted = 1 clk_mem tCES = nCS setup to nOE asserted = 0 ns

tCEH = nCS hold from nOE deasserted = 0 ns

tDSOH = MD setup to Address changing = 1.5 clk_mems plus board routing delays

tDOH = MD hold from Address changing = 0 ns

Intel® PXA255 Processor Developer’s Manual

6-51

Page 233
Image 233
Intel PXA255 manual ROM Timing Diagrams and Parameters, Clkmem