System Integration Unit

Table 4-48. PWM_PERVALn Bit Definitions

 

 

 

Physical Address

 

 

PWM Period Control Registers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x40B0_0008

 

 

 

 

 

 

System Integration Unit

 

 

 

 

 

 

 

 

 

 

(PWM_PERVAL0, PWM_PERVAL1)

 

 

 

 

 

 

 

 

 

 

0x40C0_0008

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

PV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

<31:10>

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PWMn Period Control:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

<9:0>

 

 

PV

 

The number of PSCLK_PWMn cycles that comprise one PWM_OUTn cycle

 

 

 

 

 

 

 

 

 

NOTE: If PV = 0x0, the PWMn clock (PWM_OUTn) is set high and does not toggle unless

 

 

 

 

 

 

 

 

 

 

 

FDCYCLE=0x0 and DCYCLE=0x0. In this case PWM_OUTn is set low and does

 

 

 

 

 

 

 

 

 

 

 

not toggle regardless of the value in PV.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.5.3Pulse Width Modulator Output Wave Example

Figure 4-4is an example of the output of a Pulse Width Modulator for reference.

Figure 4-4. Basic Pulse Width Waveform

3.6864 MHz

PSCLK_PWMn

PWM_OUTn

PWM_DUTYn = 6

PWM_PERVALn = 10 (+1)

PWM_PERVAL[PV] = 0xA

PWM_DUTY[FDCYCLE] = 0x0

PWM_DUTY[DCYCLE] = 0x6

PWM_CTRL[PRESCALE] = 0x0

The output waveform in Figure 4-4is created by writing PWM_PERVALn[PV] with a decimal value of 10 (11 clocks) and PWM_DUTYn[DCYCLE] with 6. Figure 4-4also shows that PWM_CTRLn[PRESCALE] is configured with a value of 0x0 loaded, which results in the PSCLK_PWMn having the same frequency as the 3.6864 MHz input clock.

Intel® PXA255 Processor Developer’s Manual

4-43

Page 147
Image 147
Intel PXA255 manual Pulse Width Modulator Output Wave Example, PWMPERVALn Bit Definitions, 0x40B00008