Memory Controller

Figure 6-22. 32-Bit Variable Latency I/O Write Timing (Burst-of-Four, Variable Wait Cycles Per Beat)

MEMCLK

 

 

 

 

nCS[0]

 

 

 

 

 

tAS

 

 

 

MA[25:2]

0

1

2

3

MA[1:0]

byte addr

byte addr

byte addr

byte addr

 

tASRW0

tASWN

 

 

 

tAH

RDF+1+Waits

tCEH

 

tCES

 

 

RDN+2

 

RRR*2+1

 

 

 

nPWE

 

 

 

 

nOE

 

 

 

 

RDnWR

 

 

 

 

RDY

 

 

 

 

 

tDSWH

tDH

 

 

 

 

 

 

MD[31:0]

D0

D1

D2

D3

DQM[3:0]

mask0

mask1

mask2

mask3

nCS[1]

 

 

 

 

In Figure 6-21and Figure 6-22, some of the parameters are defined as follows:

tAS = Address setup to nCS = 1 MEMCLK

tCES = nCS setup to nOE or nPWE = 2 MEMCLKs

tASRW0 = Address setup to nOE or nPWE low (asserted) = 3 MEMCLKs

tASRWn = Address setup to nOE or nPWE low (asserted) = RDN MEMCLKs

tDSWH,min = Minimum write data, DQM setup to nPWE high (deasserted) = (RDF+2) MEMCLKs

tDHW = Data, DQM hold after nPWE high (deasserted) = 1 MEMCLK

tDHR = Data hold required after nOE deasserted = 0 ns

tCEH = nCS held asserted after nOE or nPWE deasserted = 1 MEMCLK

tAH = Address hold after nOE or nPWE deasserted = 1 MEMCLK

nOE or nPWE high time between burst beats = (RDN+2) MEMCLKs

Intel® PXA255 Processor Developer’s Manual

6-57

Page 239
Image 239
Intel PXA255 manual RDF+1+Waits