Intel PXA255 manual RTC Counter Register Rcnr, RTC Status Register Rtsr, Rcnr Bit Definitions, Rcv

System Integration Unit

4.3.2.3RTC Counter Register (RCNR)

The RCNR, shown in Table 4-39, is a read/write register. The counter may be written by the processor at any time although it is recommended that the operating system prevent inadvertent writes to the RCNR through the use of the MMU protection mechanisms (refer to the Intel XScale® Microarchitecture for the Intel® PXA255 Processor User’s Manual for details of MMU operation.)

Because of the asynchronous nature of the HZ clock relative to the processor clock, writes to this counter are controlled by a hardware mechanism that delays the actual write to the counter after the processor store is performed by approximately two 32 kHz clock cycles. In case of multiple writes to RCNR in quick succession, the final update to the RCNR counter may be delayed by up to two 32 kHz clock cycles.

The RCNR may be read at any time. Reads reflect the value in the counter after it increments or has been written and does not have the two 32 kHz clock cycle delay.

Table 4-39. RCNR Bit Definitions

Physical Address	RCNR	System Integration Unit
0x4090_0000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RCV

Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
		Bits				Name													Description
		<31:0>				RCV			RTC Count Value.
									The current value of the RTC counter.

4.3.2.4RTC Status Register (RTSR)

The RTSR, shown in Table 4-40, is cleared to all zeroes at hardware reset. The ALE and HZE bits enable both the interrupt for the functions as well as the updating the AL and HZ bits. The AL and HZ bits are status bits and are set by the RTC logic if the ALE and HZE bits are set respectively.

They are cleared by writing ones to the AL and HZ bits. The AL and HZ bits are routed to the interrupt controller where they may be enabled to cause a first level interrupt. Write zeros to all reserved bits and ignore all reads to the reserved bits.

In Sleep mode, only AL events set the status bit in the RTSR register. The HZ bit is not set in Sleep mode since it is a recurring event.

Table 4-40shows the bitmap of the RTC Status Register.

Intel® PXA255 Processor Developer’s Manual 4-31