Intel PXA255 manual Ficp Data Register Icdr, Icrd Bit Definitions

Fast Infrared Communication Port

11.3.4FICP Data Register (ICDR)

The ICDR, shown in Table 11-5, is a 32-bit register and its lower 8 bits are the top entry of the transmit FIFO when the register is written and the bottom entry of the receive FIFO when the register is read.

Reads to ICDR access the lower 8 bits of the receive FIFO’s bottom entry. As data enters the top of the receive FIFO, bits 8 – 10 are used as tags to indicate conditions that occur as each piece of data is received. The tag bits are transferred down the FIFO with the data byte that encountered the condition. When data reaches the bottom of the FIFO, bit 8 of the FIFO entry is transferred to the end-of-frame (EOF) flag, bit 9 to the CRC error (CRE) flag, and bit 10 to the receiver overrun (ROR) flag. All these flags are in FICP status register 1. These flags can be read to determine whether the value at the bottom of the FIFO represents the frame’s last byte or an error that was encountered during reception. After the flags are checked, the FIFO value can be read. This causes the data in the next location of the receive FIFO to be transferred to the bottom entry and its EOF, CRE, and ROR bits to be transferred to the status register.

The end/error in FIFO (EIF) flag is set in status register 0 when a tag bit is set in any of the receive FIFO’s bottom eight, 16, or 32 entries, as determined by the trigger level. The EIF flag is cleared when no error bits are set in the FIFO’s bottom entries. When EIF is set, an interrupt is generated and the receive FIFO DMA request is disabled. Software must empty the FIFO and check for the EOF, CRE, and ROR error flags in ICSR1 before it removes each data value from the FIFO. After each entry is removed, the EIF bit must be checked to determine if any set end or error tag remains and the procedure is repeated until all set tags are flushed from the FIFO’s bottom entries. When EIF is cleared, DMA service for the receive FIFO is re-enabled.

Both FIFOs are cleared when the processor is reset. The transmit FIFO is cleared when TXE is 0. The receive FIFO is cleared when RXE is 0.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 11-5. ICRD Bit Definitions

				0x4080_000C							Fast Infrared Communication Port											Fast Infrared Communication Port
													Data Register (ICDR)
Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

reserved

DATA

Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
		Bits				Name													Description
		[31:8]					—		reserved
									Top/bottom of transmit/receive FIFO.
		[7:0]				DATA			Read - Read data from front of receive FIFO
									Write - Place data at end of transmit FIFO

11-12 Intel® PXA255 Processor Developer’s Manual