Intel manual Pin & Signal Descriptions for the PXA255 Processor Sheet 2

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)

Pin Name	Type	Signal Descriptions	Reset State	Sleep State
SDCLK[1]	OCZ	SDRAM Clocks (output) Connect SDCLK[1] and	Driven Low	Driven Low
		SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1
		and 2/3, respectively. They are driven by either the
		internal memory controller clock, or the internal memory
		controller clock divided by 2. At reset, all clock pins are
SDCLK[2]	OC	free running at the divide by 2 clock speed and may be	Driven Low	Driven Low
		turned off via free running control register bits in the
		memory controller. The memory controller also provides
		control register bits for clock division and deassertion of
		each SDCLK pin. SDCLK[2:1] control register assertion
		bits are always deasserted upon reset.
nCS[5]/	ICOCZ
GPIO[33]
nCS[4]/	ICOCZ
GPIO[80]
		Static chip selects. (output) Chip selects to static
nCS[3]/			Pulled High -
	ICOCZ	memory devices such as ROM and Flash. Individually		Note [4]
GPIO[79]		programmable in the memory configuration registers.	Note[1]
		nCS[5:0] can be used with variable latency I/O devices.
nCS[2]/	ICOCZ
GPIO[78]
nCS[1]/	ICOCZ
GPIO[15]
nCS[0]	ICOCZ	Static chip select 0. (output) Chip select for the boot	Driven High	Note [4]
		memory. nCS[0] is a dedicated pin.
RD/nWR	OCZ	Read/Write for static interface. (output) Signals that the	Driven Low	Holds last state
		current transaction is a read or write.
RDY/		Variable Latency I/O Ready pin. (input) Notifies the	Pulled High -
	ICOCZ	memory controller when an external bus device is ready		Note [3]
GPIO[18]			Note[1]
		to transfer data.
		LCD display data. (output) Transfers pixel information
L_DD[8]/		from the LCD Controller to the external LCD panel.	Pulled High -
	ICOCZ	Memory Controller alternate bus master request.		Note [3]
GPIO[66]			Note[1]
		(input) Allows an external device to request the system
		bus from the Memory Controller.
		LCD display data. (output) Transfers pixel information
L_DD[15]/	ICOCZ	from the LCD Controller to the external LCD panel.	Pulled High -	Note [3]
GPIO[73]		Memory Controller grant. (output) Notifies an external	Note[1]
		device that it has been granted the system bus.
MBGNT/	ICOCZ	Memory Controller grant. (output) Notifies an external	Pulled High -	Note [3]
GP[13]		device that it has been granted the system bus.	Note[1]
MBREQ/		Memory Controller alternate bus master request.	Pulled High -
	ICOCZ	(input) Allows an external device to request the system		Note [3]
GP[14]			Note[1]
		bus from the Memory Controller.
PCMCIA/CF Control Pins
nPOE/	ICOCZ	PCMCIA output enable. (output) Reads from PCMCIA	Pulled High -	Note [5]
GPIO[48]		memory and to PCMCIA attribute space.	Note[1]
nPWE/		PCMCIA write enable. (output) Performs writes to	Pulled High -
	ICOCZ	PCMCIA memory and to PCMCIA attribute space. Also		Note [5]
GPIO[49]			Note[1]
		used as the write enable signal for Variable Latency I/O.

2-10 Intel® PXA255 Processor Developer’s Manual