Intel manual Coprocessor 15 Register 1 P-Bit, ID Bit Definitions, PXA255 Processor ID Values

System Architecture

Table 2-2. ID Bit Definitions

Bit

Reset

		CP15 Register 0													ID												CP15
31 30 29 28 27					26		25 24 23			22 21 20			19	18 17 16 15				14 13 12				11	10	9	8	7	6	5	4	3	2	1	0
			Implementation	Trademark								Architecture	Version				Core		generation		Core	Revision				Product	Number				Product	Revision
0	1	1	0	1	0		0	1	0	0	0	0	0	1	0	1	0		0	1	0	0	0	0	1	0	0	0	0	0	0	0	0
	[31:24]				Implementation							Implementation trademark.
							Trademark					0x69 – Intel® Corporation.
	[23:16]					Architecture						ARM* Architecture version of the core.
							Version					0x05 – ARM* Architecture version 5TE
												This field is updated when new sets of features are added to the core. This
	[15:13]				Core Generation							allows software that is dependant on core features to target a specific core.
												Core generation:
												0b001 – Intel XScale® core
												This field is updated each time a core is revised. Differences may include
												errata, software workarounds, etc.
	[12:10]				Core Revision							Core revision:
												0b000 – First version of the core.
												0b010 – Third version of the core.
												0b011 – Fourth version of the core.
	[9:4]				Product Number							Product Number
												0b010000 – PXA255 processor
												This field tracks the different steppings for each ASSP.
	[3:0]				Product Revision							Product Revision
												0b0110 – A0 Stepping

Table 2-3. PXA255 Processor ID Values

Stepping	ARM ID	JTAG ID
A0	0x6905_2D06	0x6926_4013

2.2.5Coprocessor 15 Register 1 - P-Bit

Bit 1 of this register is defined as the Page Table Memory Attribute bit or P-bit. It is not implemented in the processor and must be written as zero. Similarly, the P-bit in the page table descriptor in the MMU is not implemented and must be written to zero.

2-4 Intel® PXA255 Processor Developer’s Manual