Intel PXA255 manual Fifo Control Register FCR, Interrupt Identification Register Decode Sheet 2

								Hardware UART
Table 17-9. Interrupt Identification Register Decode (Sheet 2 of 2)
Interrupt ID bits							Interrupt SET/RESET Function
	3	2	1	0	Priority	Type	Source	RESET Control
IID[00]	0	0	0	0	Fourth	Modem Status	Clear to send, data set ready, ring	Reading the Modem Status register.
					Highest		indicator, received line signal detect.
							Non Prioritized Interrupts:
ABL		4			None	Autobaud Lock	Autobaud circuitry has locked onto	Reading the IIR register
						indication.	the baud rate.

17.5.6FIFO Control Register (FCR)

The FCR, shown in Table 17-10, is a write-only register that is located at the same address as the IIR, which is a read-only register. The FCR enables/disables the transmitter/receiver FIFOs, clears the transmitter/receiver FIFOs, and sets the receiver FIFO trigger threshold.

This is a write-only register. Write zeros to reserved bits.

Table 17-10. FCR Bit Definitions (Sheet 1 of 2)

Physical Address	FIFO Control Register (FCR)	PXA255 Processor Hardware UART
0x4160_0008

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

reserved ITL reserved TIL RESETTF

Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? ? 0 0

1

RESETRF

0

0

TRFIFOE

0

Bits	Name	Description
31:8	—	reserved
		Interrupt Trigger Level (threshold) – When the number of bytes in the receiver FIFO equals
		the interrupt trigger threshold programmed into this field and the received data available
		interrupt is enabled via the IER, an interrupt is generated and appropriate bits are set in the
7:6	ITL	IIR. The receive DMA request is also generated when the trigger threshold is reached.
		0b00 – 1 byte or more in FIFO causes interrupt (not valid in DMA mode)
		0b01 – 8 bytes or more in FIFO causes interrupt and DMA request
		0b10 – 16 bytes or more in FIFO causes interrupt and DMA request
		0b11 – 32 bytes or more in FIFO causes interrupt and DMA request
5:4	—	reserved
		Transmitter Interrupt Level – Determines when interrupts or DMA requests are sent from the
3	TIL	transmit FIFO.
		0 = Interrupt/DMA request when FIFO is half empty.
		1 = Interrupt/DMA request when FIFO is empty
		Reset Transmitter FIFO – When RESETTF is set to 1, all the bytes in the transmitter FIFO
		are cleared. The TDRQ bit in the LSR is set and the IIR shows a transmitter requests data
2	RESETTF	interrupt, if the TIE bit in the IER is set. The Transmitter Shift register is not cleared and it
		completes the current transmission.
		0 = Writing 0 has no effect
		1 = The transmitter FIFO is cleared

Intel® PXA255 Processor Developer’s Manual 17-15