DMA Controller

Table 5-7. DCSRx Bit Definitions (Sheet 1 of 2)

Physical Address

DMA Channel Control/Status

DMA Controller

0x4000_0000 - 0x4000_003C

Register (DCSRx)

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

 

RUN

 

NODESCFETCH

 

STOPIRQEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REQPEND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

3

2

1

0

STOPSTATE

 

ENDINTR

 

STARTINTR

 

BUSERRINTR

 

 

 

 

 

 

 

 

 

 

1

0

0

0

Bits

Name

Description

 

 

 

 

 

Run Bit (read / write).

 

 

0 – stops the channel

 

 

1 – starts the channel

 

 

Lets software start or stop the channel. If the run bit is cleared in the middle of the burst, the

 

 

burst will complete before the channel is stopped.

31

RUN

Software must write to DDADRx before it sets this bit for Descriptor Fetch Mode.

After the channel stops, the DCSR[STOPSTATE] bit is set to 1. Software must poll the

 

 

 

 

DCSR[STOPSTATE] bit to determine the channel’s status or set the STOPIRQEN to force

 

 

an interrupt after the channel stops. Software must write a 1 to the bit to restart a stopped

 

 

channel.

 

 

After clearing the run bit to stop the channel, an end interrupt is not guaranteed to happen if

 

 

the length bits, DCMDx[LENGTH], is zero. Software must determine if the transfer is done

 

 

after clearing the run bit.

 

 

 

 

 

No-Descriptor Fetch (read / write).

 

 

0 – Descriptor Fetch Mode

 

 

1 – No-Descriptor Fetch Mode

30

NODESC

Determines if the channel has a descriptor.

FETCH

If this bit is set to a 0, the channel is in Descriptor Fetch Mode. See Section 5.1.4.2 for

 

 

 

information on the DMAC registers.

 

 

If this bit is set to a 1, the channel is in No-Descriptor Fetch Mode. See Section 5.1.4.1 for

 

 

information on the DMAC registers.

 

 

 

 

 

Stop Interrupt Enable (read / write).

 

 

0 – no interrupt if the channel is in uninitialized or stopped state

29

STOPIRQEN

1 – enables an interrupt if the channel is in uninitialized or stopped state

Allows an interrupt to pass to the interrupt controller if the DCSR[STOPSTATE] bit is 1. If

 

 

 

 

the DCSR[STOPINTEN] bit is 0, the interrupt is not generated after the channel stops. If

 

 

software writes a 1 to this bit before the channel starts, an interrupt is generated.

 

 

 

28:9

reserved

 

 

 

 

 

Request Pending (read-only).

8

REQPEND

0 – no pending request

1 – the channel has a pending request

 

 

 

 

Indicates that the DMA channel has a pending request.

 

 

 

7:4

reserved

 

 

 

5-18

Intel® PXA255 Processor Developer’s Manual

Page 168
Image 168
Intel PXA255 manual DCSRx Bit Definitions Sheet 1, Run, Reqpend, Stopstate Endintr Startintr Buserrintr