Intel PXA255 manual Network SSP Serial Port Register Summary, Nssp Register Address Map, Ssdr

Network SSP Serial Port

As the system accesses the register, FIFO control logic transfers data automatically between the registers and FIFOs as fast as the system moves it. Unless attempting a write to a full transmit FIFO, data in the FIFO shifts up or down to accommodate the new word(s). Status bits show users whether the FIFO is full, above the programmable trigger threshold, below the programmable trigger threshold or empty.

For transmit data transfers, the register can be written by the system processor anytime it falls below its trigger threshold when using programmed I/O.

When a data size of less than 32-bits is selected, do not left-justify data written to the transmit FIFO. Transmit logic left-justifies the data and ignores any unused bits. Received data of less than 32-bits is automatically right-justified in the receive FIFO.

When the SSP is programmed for the Microwire* protocol and the size of the Transmit data is eight bits (SSCR1[MWDS] cleared), the most significant bits are ignored. Similarly, if the size for the Transmit data is 16 bits (SSCR1[MWDS] set), the most significant 16 bits are ignored. SSCR0[DSS] controls the Receive data size.

Both FIFOs are cleared when the port is reset, or by clearing SSCR0[SSE].

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 16-9. SSDR Bit Definitions

				0x4140_0010											SSDR							Network SSP Serial Port
Bit
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15 14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
																DATA
Reset	? ? ? ? ? ? ? ?								?	?	?	?	? ? ? ? ? ?					?	?	?	?	? ? ? ? ? ? ? ? ? ?
		Bits				Name												Description
		31:0				DATA			TRANSMIT/RECEIVE DATA:
									Data word to be written to/read from Transmit/receive FIFO

16.6Network SSP Serial Port Register Summary

Table 16-10shows the registers associated with the NSSP and their physical addresses.

Table 16-10. NSSP Register Address Map

Physical Address	Name	Description
0x4140_0000	NSSCR0	NSSP Control register 0
0x4140_0004	NSSCR1	NSSP Control register 1
0x4140_0008	NSSSR	NSSP Status register
0x4140_000C	NSSITR	NSSP Interrupt Test register
0x4140_0010	NSSDR	NSSP Data Write Register / Data Read register
0x4140_0028	NSSTO	NSSP Time Out register
0x4140_002C	NSSPSP	NSSP Programmable Serial Protocol

Intel® PXA255 Processor Developer’s Manual 16-29