Fast Infrared Communication Port

11.3.6FICP Status Register 1 (ICSR1)

ICSR1, shown in Table 11-7, contains flags that indicate that the receiver is synchronized, the transmitter is active, the transmit FIFO is not full, the receive FIFO is not empty, and that an EOF, CRE, or underrun error has occurred.

This is a read-only register. Ignore reads from reserved bits.

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Table 11-7. ICSR1 Bit Definitions

0x4080_0018

Fast Infrared Communication Port

Fast Infrared Communication Port

Status Register 1 (ICSR1)

 

 

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7

reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6 5 4 3 2 1 0

ROR CRE EOF TNF RNE TBY RSY

0 0 0 1 0 0 0

Bits

Name

Description

 

 

 

[31:7]

reserved

 

 

 

 

 

Receive FIFO overrun (read-only).

 

 

0 = Receive FIFO has not experienced an overrun.

6

ROR

1 = Receive logic attempted to place data into receive FIFO while it was full. Data received

after the FIFO is full are lost.

 

 

 

 

Each time an 11-bit value reaches the bottom of the receive FIFO, bit 10 from the last FIFO

 

 

entry is transferred to the ROR bit.

 

 

 

 

 

CRC error (read-only).

 

 

0 = CRC not encountered yet or no CRC check errors encountered in the receipt of data.

5

CRE

1 = CRC calculated on the incoming data. Does not match CRC value contained within

the received frame.

 

 

 

 

Each time an 11-bit value reaches the bottom of the receive FIFO, bit 9 from the last FIFO

 

 

entry is transferred to the CRE bit.

 

 

 

 

 

End of frame (read-only).

 

 

0 = Current frame has not completed.

4

EOF

1 = The value at the bottom of the receive FIFO is the last byte of data within the frame,

including aborted frames.

 

 

 

 

Each time an 11-bit value reaches the bottom of the receive FIFO, bit 8 from the last FIFO

 

 

entry is transferred to the EOF bit.

 

 

 

3

TNF

Transmit FIFO not full (read-only).

0 = Transmit FIFO is full.

 

 

1 = Transmit FIFO is not full (no interrupt generated).

 

 

 

 

 

Receive FIFO not empty (read-only).

2

RNE

0 = Receive FIFO is empty.

 

 

1 = Receive FIFO is not empty (no interrupt generated).

 

 

 

 

 

Transmitter busy flag (read-only).

1

TBY

0 = Transmitter is idle (continuous preambles) or disabled.

1 = Transmit logic is currently transmitting a frame (address, control, data, CRC, or start/

 

 

 

 

stop flag). No interrupt generated.

 

 

 

0

RSY

Receiver synchronized flag (read-only).

0 = Receiver is in hunt mode or is disabled.

 

 

1 = Receiver logic is synchronized with the incoming data (no interrupt generated).

 

 

 

Intel® PXA255 Processor Developer’s Manual

11-15

Page 401
Image 401
Intel PXA255 manual Ficp Status Register 1 ICSR1, ICSR1 Bit Definitions