LCD Controller

Figure 7-1illustrates a simplified, top-level block diagram for the processor LCD Controller.

Figure 7-1. LCD Controller Block Diagram

System Bus

From Clock Module LCDClk

Control signals

LCD DMA Controller

Pixel Data Register Data

Configuration

Input FIFOs

Encoded pixel data

Raw pixel data

Palette RAM

Raw pixel

Raw

data

pixel

 

data

 

Raw

 

pixel data

 

TMED

 

Dithering

 

Engine

 

Dithered

 

pixels

Registers

Serializer

Output FIFOs

L_DD[15:0]

To Pins

Intel® PXA255 Processor Developer’s Manual

7-3

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Image 267
Intel PXA255 manual LCD Controller Block Diagram