I2C Bus Interface Unit

Table 9-11. ISR Bit Definitions (Sheet 2 of 2)

 

 

 

Physical Address

 

 

 

 

I2C Status Register

 

 

 

 

 

 

 

I2C Bus Interface Unit

 

 

 

 

 

 

 

4030_1698

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

 

2

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BED

 

SAD

 

GCAD

 

IRF

 

ITE

 

ALD

 

SSD

 

IBB

 

UB

 

ACKNAK

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ACK/NAK Status:

0 = I2C unit received or sent an ACK on the bus.

1 ACKNAK 1 = I2C unit received or sent a NAK.

Used in slave-transmit mode to determine when the transferred byte is the last one. Updated after each byte and ACK/NAK information is received.

 

 

Read/Write Mode:

0

RWM

0 =

I2C unit is in master-transmit or slave-receive mode.

1 =

I2C unit is in master-receive or slave-transmit mode.

R/nW bit of the slave address. Automatically cleared by hardware after a stop state.

0

RWM

0

9.9.5I2C Slave Address Register (ISAR)

The ISAR, shown in Table 9-12, defines the I2C unit’s 7-bit slave address. In slave-receive mode, the processor responds when the 7-bit address matches the value in this register. The processor writes this register before it enables I2C operations. The ISAR is fully programmable (no address is assigned to the I2C unit) so it can be set to a value other than those of hard-wired I2C slave peripherals in the system. If the processor is reset, the ISAR is not affected. The ISAR register default value is 00000002.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 9-12. ISAR Bit Definitions

 

 

 

Physical Address

 

 

 

I2C Slave Address Register

 

 

 

 

I2C Bus Interface Unit

 

 

 

 

 

 

 

4030_16A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31:7

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6:0

 

 

ISA

 

I2C Slave Address: 7-bit address that the I2C unit responds to when in slave-receive

 

 

 

 

 

 

mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Intel® PXA255 Processor Developer’s Manual

9-27

Page 357
Image 357
Intel PXA255 manual 5 I2C Slave Address Register Isar, ISR Bit Definitions Sheet 2, Isar Bit Definitions