Memory Controller

Table 6-5. MDREFR Bit Definitions (Sheet 2 of 3)

 

 

 

 

0x4800_0004

 

 

 

 

 

 

MDREFR

 

 

 

 

 

 

Memory Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

K2FREE

K1FREE

K0FREE

SLFRSH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

1

1

1

1

 

 

 

 

 

 

 

 

 

 

 

reserved

0

APDK2DB2K2RUNK1DB2K1RUNE1PINK0DB2K0RUNE0PIN

0 1 0 1 0 0 1 * * 1 1

DRI

1 1 1 1 1 1 1 1 1 1

Bits

Name

 

Description

 

 

 

 

 

SDRAM Clock Pin 2 (SDCLK<2>) Run Control/Status

 

 

0 –

SDCLK2 disabled

 

 

1 –

SDCLK2 enabled

18

K2RUN

K2RUN also can be cleared by program. Use with caution because the resulting state

 

 

prohibits automatic transitions for any commands.

 

 

Setting K1RUN and/or K2RUN is a part of the hardware and sleep reset procedure for

 

 

SDRAM.

 

 

 

 

 

SDRAM Clock Pin 1 (SDCLK1) Divide by 2 Control/Status

17

K1DB2

0 –

SDCLK1 is same frequency as MEMCLK

 

 

1 – SDCLK1 runs at one-half the MEMCLK frequency

 

 

 

 

 

SDRAM Clock Pin 1 (SDCLK<1>) Run Control/Status

 

 

0 –

SDCLK1 disabled

 

 

1 –

SDCLK1 enabled

16

K1RUN

K1RUN can be cleared by software. Use with caution because the resulting state prohibits

 

 

automatic transitions for any commands.

 

 

Setting K1RUN and/or K2RUN is a part of the hardware and sleep reset procedure for

 

 

SDRAM.

 

 

 

 

 

SDRAM Clock Enable Pin 1 (SDCKE1) Level Control/Status

 

 

0 – SDCKE1 is disabled

 

 

1 – SDCKE1 is enabled

15

E1PIN

E1PIN can be cleared by program to cause a power-down command (if K1RUN=1 and/or

K2RUN=1, and SLFRSH=0). Use with caution because the resulting state prohibits

 

 

automatic transitions for mode register set, read, write, and refresh commands. E1PIN can

 

 

be set by program to cause a power-down-exit command (if K1RUN=1 and/or K2RUN=1,

 

 

and SLFRSH=0).

 

 

Setting E1PIN is a part of the hardware reset or sleep reset procedure for SDRAM.

 

 

 

 

 

Synchronous Static Memory Clock Pin 0 (SDCLK<0>) Divide by 2 Control/Status

14

K0DB2

0 – SDCLK0 runs at the memory clock frequency.

1 – SDCLK0 runs at one-half the memory clock frequency.

 

 

This bit is automatically set upon hardware or sleep reset.

6-16

Intel® PXA255 Processor Developer’s Manual

Page 198
Image 198
Intel PXA255 manual Mdrefr Bit Definitions Sheet 2, 0 1 0 0 1 * * 1, 1 1 1 1 1 1 1