USB Device Controller

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This section describes the Universal Serial Bus (USB) protocol and its implementation-specific options for device controllers for the PXA255 processor. These options include endpoint number, type, and function; interrupts to the core; and a transmit/receive FIFO interface. A working knowledge of the USB standard is vital to using this section effectively. The Universal Serial Bus Device Controller (UDC) is USB-compliant and supports all standard device requests issued by the host. UDC operation summaries and quick reference tables are provided. Refer to the Universal Serial Bus Specification, revision 1.1, for a full description of the USB protocol. The Universal Serial Bus Specification is available at http://www.usb.org.

12.1USB Overview

The UDC supports 16 endpoints and can operate half-duplex at a rate of 12 Mbps (as a slave only, not as a host or hub controller). The UDC supports four device configurations. Configurations 1, 2, and 3 each support two interfaces. Alternate interface settings are not supported. This allows the host to accommodate dynamic changes in the physical bus topology. A configuration is a specific combination of USB resources available on the device. An interface is a related set of endpoints that present a device feature or function to the host.

The UDC transmits serial information that contains layers of communication protocols. Fields are the most basic protocol. UDC fields include: sync, packet identifier (PID), address, endpoint, frame number, data, and Cyclic Redundancy Check (CRC). Fields are combined to produce packets. A packet’s function determines the combination and number of fields that make up the packet. Packet types include: token, start of frame, data, and handshake. Packets are assembled into groups to produce transactions. Transactions fall into four groups: bulk, control, interrupt, and isochronous. Endpoint 0 is used only to communicate the control transactions that configure the UDC. Endpoint 0’s responsibilities include: connection, address assignment, endpoint configuration, bus enumeration, and disconnection.

The UDC uses a dual-port memory to support FIFO operations. Each Bulk and Isochronous Endpoint FIFO structure is double buffered to enable the endpoint to process one packet as it assembles another. The DMA and the Megacell can fill and empty the FIFOs. An interrupt or DMA service request is generated when a packet has been received. The DMA engine services the UDC FIFOs in 32-byte increments. Interrupts are also generated when the FIFO encounters a short packet or zero-length packet. Endpoint 0 has a 16-entry long, 8-bit wide FIFO that can only be read or written by the processor.

For endpoints 1-15, the UDC uses its dual-ported memory to hold data for a Bulk OUT transaction while the transaction is checked for errors. If the Bulk OUT transaction data is invalid, the UDC sends a NAK handshake to request the host to resend the data. The software is not notified that the OUT data is invalid until the Bulk OUT data is received and verified. If the host sends a NAK handshake in response to a Bulk IN data transmission, the UDC resends the data. Because the FIFO maintains a copy of the data, the software does not have to reload the data.

The external pins dedicated to the UDC interface are UDC+ and UDC-. The USB protocol uses differential signalling between the two pins for half-duplex data transmission. A 1.5 kΩ pull-up resistor must be connected to the USB cable’s D+ signal to pull the UDC+ pin high when it is not driven. Pulling the UDC+ pin high when it is not driven allows the UDC to be a high-speed,

Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual USB Device Controller, USB Overview