Intel PXA255 Fifo Control Register FCR, Interrupt Identification Register Decode Sheet 2, Itl

UARTs

Table 10-10. Interrupt Identification Register Decode (Sheet 2 of 2)

Interrupt ID Bits						Interrupt SET/RESET Function
							FIFO mode only: At least
				Second	Character		one character is in the	Reading the Receiver FIFO,
1	1	0	0		Timeout		Receive FIFO and no data	setting FCR[RESETRF] or
				Highest
					Indication		has been sent for four	a new start bit is received
							character times.
							Non-FIFO mode: Transmit	Non-FIFO mode: Reading
							Holding register empty	the IIR Register (if the
								source of the interrupt) or
								writing into the Transmit
0	0	1	0	Third	Transmit FIFO			Holding Register
				Highest	Data Request
							FIFO mode: Transmit has	FIFO mode: Reading the
							half, or less than half, data	IIR Register (if the source of
								the interrupt) or writing to
								the Transmitter FIFO
				Fourth			Clear to Send, Data Set	Reading the Modem Status
0	0	0	0		Modem Status		Ready, Ring Indicator, Data	Register
				Highest
							Carrier Detect

10.4.2.6FIFO Control Register (FCR)

The FCR, shown in Table 10-11, is a write-only register that is located at the same address as the IIR, which is a read-only register. The FCR enables/disables the transmitter/receiver FIFOs, clears the transmitter/receiver FIFOs, and sets the receiver FIFO trigger level.

This is a write-only register. Write zeros to reserved bits.

Table 10-11. FCR Bit Definitions (Sheet 1 of 2)

Base+0x08 FIFO Control Register UART

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6
																									ITL
												reserved
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

5	4	3	2	1		0
			RESETTF		RESETRF		TRFIFOE
reserved	reserved	reserved
0	0	0	0	0		0

Bits	Name	Description
31:8	—	reserved

Interrupt Trigger Level: When the number of bytes in the receiver FIFO equals the interrupt trigger level programmed into this field and the Received Data Available Interrupt is enabled via the IER, an interrupt is generated and appropriate bits are set in the IIR. The receive DMA request is also generated when the trigger level is reached.

7:6	ITL	0b00	– 1 byte or more in FIFO causes interrupt (Not valid in DMA mode)
		0b01	– 8 bytes or more in FIFO causes interrupt and DMA request
		0b10	– 16 bytes or more in FIFO causes interrupt and DMA request
		0b11 – 32 bytes or more in FIFO causes interrupt and DMA request
5:3	—	reserved

10-12 Intel® PXA255 Processor Developer’s Manual