System Architecture

Table 2-8. System Architecture Register Address Summary (Sheet 3 of 12)

 

 

 

 

Unit

Address

Register Symbol

Register Description

 

 

 

 

 

0x4000_024C

DCMD4

DMA Command Address Register Channel 4

 

 

 

 

 

0x4000_0250

DDADR5

DMA Descriptor Address Register Channel 5

 

 

 

 

 

0x4000_0254

DSADR5

DMA Source Address Register Channel 5

 

 

 

 

 

0x4000_0258

DTADR5

DMA Target Address Register Channel 5

 

 

 

 

 

0x4000_025C

DCMD5

DMA Command Address Register Channel 5

 

 

 

 

 

0x4000_0260

DDADR6

DMA Descriptor Address Register Channel 6

 

 

 

 

 

0x4000_0264

DSADR6

DMA Source Address Register Channel 6

 

 

 

 

 

0x4000_0268

DTADR6

DMA Target Address Register Channel 6

 

 

 

 

 

0x4000_026C

DCMD6

DMA Command Address Register Channel 6

 

 

 

 

 

0x4000_0270

DDADR7

DMA Descriptor Address Register Channel 7

 

 

 

 

 

0x4000_0274

DSADR7

DMA Source Address Register Channel 7

 

 

 

 

 

0x4000_0278

DTADR7

DMA Target Address Register Channel 7

 

 

 

 

 

0x4000_027C

DCMD7

DMA Command Address Register Channel 7

 

 

 

 

 

0x4000_0280

DDADR8

DMA Descriptor Address Register Channel 8

 

 

 

 

 

0x4000_0284

DSADR8

DMA Source Address Register Channel 8

 

 

 

 

 

0x4000_0288

DTADR8

DMA Target Address Register Channel 8

 

 

 

 

 

0x4000_028C

DCMD8

DMA Command Address Register Channel 8

 

 

 

 

 

0x4000_0290

DDADR9

DMA Descriptor Address Register Channel 9

 

 

 

 

 

0x4000_0294

DSADR9

DMA Source Address Register Channel 9

 

 

 

 

 

0x4000_0298

DTADR9

DMA Target Address Register Channel 9

 

 

 

 

 

0x4000_029C

DCMD9

DMA Command Address Register Channel 9

 

 

 

 

 

0x4000_02A0

DDADR10

DMA Descriptor Address Register Channel 10

 

 

 

 

 

0x4000_02A4

DSADR10

DMA Source Address Register Channel 10

 

 

 

 

 

0x4000_02A8

DTADR10

DMA Target Address Register Channel 10

 

 

 

 

 

0x4000_02AC

DCMD10

DMA Command Address Register Channel 10

 

 

 

 

 

0x4000_02B0

DDADR11

DMA Descriptor Address Register Channel 11

 

 

 

 

 

0x4000_02B4

DSADR11

DMA Source Address Register Channel 11

 

 

 

 

 

0x4000_02B8

DTADR11

DMA Target Address Register Channel 11

 

 

 

 

 

0x4000_02BC

DCMD11

DMA Command Address Register Channel 11

 

 

 

 

 

0x4000_02C0

DDADR12

DMA Descriptor Address Register Channel 12

 

 

 

 

 

0x4000_02C4

DSADR12

DMA Source Address Register Channel 12

 

 

 

 

 

0x4000_02C8

DTADR12

DMA Target Address Register Channel 12

 

 

 

 

 

0x4000_02CC

DCMD12

DMA Command Address Register Channel 12

 

 

 

 

 

0x4000_02D0

DDADR13

DMA Descriptor Address Register Channel 13

 

 

 

 

 

0x4000_02D4

DSADR13

DMA Source Address Register Channel 13

 

 

 

 

 

0x4000_02D8

DTADR13

DMA Target Address Register Channel 13

 

 

 

 

 

0x4000_02DC

DCMD13

DMA Command Address Register Channel 13

 

 

 

 

 

0x4000_02E0

DDADR14

DMA Descriptor Address Register Channel 14

 

 

 

 

 

0x4000_02E4

DSADR14

DMA Source Address Register Channel 14

 

 

 

 

 

0x4000_02E8

DTADR14

DMA Target Address Register Channel 14

 

 

 

 

Intel® PXA255 Processor Developer’s Manual

2-23

Page 53
Image 53
Intel PXA255 manual System Architecture Register Address Summary Sheet 3