System Architecture

Figure 2-3. Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF

0x7FFF FFFF 0x7C00_0000 0x7800_0000 0x7400_0000 0x7000_0000 0x6C00_0000 0x6800_0000 0x6400_0000 0x6000_0000 0x5C00_0000 0x5800_0000 0x5400_0000 0x5000_0000 0x4C00_0000 0x4800_0000 0x4400_0000 0x4000_0000

0x3C00_0000 0x3800_0000 0x3400_0000 0x3000_0000 0x2C00_0000 0x2800_0000 0x2400_0000 0x2000_0000 0x1C00_0000 0x1800_0000 0x1400_0000 0x1000_0000 0x0C00_0000 0x0800_0000

0x0400_0000

0x0000_0000

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Memory Mapped registers (Memory Ctl)

Memory Mapped registers (LCD)

Memory Mapped registers (Peripherals)

PCMCIA/CF- Slot 1 (256 MB)

PCMCIA/CF - Slot 0 (256MB)

Reserved (64 MB)

Reserved (64 MB)

Static Chip Select 5 (64 MB)

Static Chip Select 4 (64 MB)

Static Chip Select 3 (64 MB)

Static Chip Select 2 (64 MB)

Static Chip Select 1 (64 MB)

Static Chip Select 0 (64 MB)

2-20

Intel® PXA255 Processor Developer’s Manual

Page 50
Image 50
Intel PXA255 manual Memory Map Part Two From 0x00000000 to 0x7FFF Ffff