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Intel PXA255 manual Motorola SPI* Frame Protocol multiple transfers, Serial Clock Phase SPH

Models: PXA255

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Network SSP Serial Port

Figure 16-3. Motorola SPI* Frame Protocol (multiple transfers)

SSPSCLK

SSPSFRM

SSPTX Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0]

SSPRX Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0]

A9651-01

Note: When configured as either master or slave (to clock or frame) the SSP continues to drive SSPTXD with the last bit of data sent (the LSB). If SSCR0[SSE] is cleared, SSPTXD goes low. The state of SSPRXD is undefined before the MSB and after the LSB is transmitted. For minimum power consumption, this pin must not float.

Note: The phase and polarity of SSPSCLK can be configured for four different modes. This example shows just one of those modes (SSCR1[SPO] = 0, SSCR1[SPH] = 0).

Figure 16-4. Motorola SPI* Frame Protocol (single transfers)

SSPSCLK

SSPSFRM

SSPTXD		Bit[N]	Bit[N-1]	Bit[1]	Bit[0]	End of Transfer Data State
SSPRXD	Undefined	Bit[N]	Bit[N-1]	Bit[1]	Bit[0]	Undefined
		MSB	4 to 32 Bits		LSB

A9519-02

Note: When configured as either master or slave (to clock or frame) the SSP continues to drive SSPTXD with the last bit of data sent (the LSB). If SSCR0[SSE] is cleared, SSPTXD goes low. The state of SSPRXD is undefined before the MSB and after the LSB is transmitted. For minimum power consumption, this pin must not float.

16.4.3.2.1Serial Clock Phase (SPH)

The phase relationship between the SSPSCLK and the serial frame (SSPSFRM) pins when the Motorola SPI* protocol is selected is controlled by SSCR1[SPH].

When SPH is cleared, SSPSCLK remains in its inactive or idle state (as determined by SSCR1[SPO]) for one full cycle after SSPSFRM is asserted low at the beginning of a frame. SSPSCLK continues to transition for the rest of the frame. It is then held in its inactive state for one-half of an SSPSCLK period before SSPSFRM is de-asserted high at the end of the frame.

Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual Motorola SPI* Frame Protocol multiple transfers, Serial Clock Phase SPH

Contents

Intel PXA255 Processor Intel PXA255 Processor Developer’s Manual Contents Power Manager General Configuration Register Pcfr Contents Expansion Card Interface Timing Diagrams and Parameters DMA 10-1 11-1 12.6 14.3 15.5 Figures BitBurst-of-Eight ROM or Flash Read Timing Diagram MSC0RDF = 10-25 Tables Clocks Manager Register Summary Sxcnfg 10-6 10-8 12-26 15-7 Date Revision Description Revision HistoryXxiv System Integration Features Intel XScale Microarchitecture FeaturesClocks and Power Controllers Memory ControllerUniversal Serial Bus USB Client LCD Controller DMA Controller Dmac6 AC97 Controller Inter-IC Sound I2S ControllerInter-Integrated Circuit I2C Bus Interface Unit Synchronous Serial Protocol Controller SspcGpio UARTsReal-Time Clock RTC OS TimersPulse-Width Modulator PWM Interrupt ControlIntroduction Overview System ArchitectureCoprocessor 7 Register 4 Psfs Bit Intel XScale Microarchitecture Implementation OptionsCPU Core Fault Register Bit Definitions Coprocessor 14 Register 6 and 7- Clock and Power ManagementCoprocessor 14 Registers 0-3 Performance Monitoring Coprocessor 15 Register 0 ID Register DefinitionID Bit Definitions Coprocessor 15 Register 1 P-BitPXA255 Processor ID Values ARM ID Jtag IDI/O Ordering SemaphoresInterrupts Unit Sleep Mode Gpio Reset Watchdog Reset Hard Reset ResetUSB ICPSelecting Peripherals vs. General Purpose I/O Internal RegistersPower Management Power on Reset and Boot OperationPin List Processor Pin TypesPin Name Type Signal Descriptions Reset State Sleep State Pin & Signal Descriptions for the PXA255 Processor Sheet 1Pin & Signal Descriptions for the PXA255 Processor Sheet 2 Psktsel Pin & Signal Descriptions for the PXA255 Processor Sheet 3Pin & Signal Descriptions for the PXA255 Processor Sheet 4 Pin & Signal Descriptions for the PXA255 Processor Sheet 5 Pin & Signal Descriptions for the PXA255 Processor Sheet 6 Pin & Signal Descriptions for the PXA255 Processor Sheet 7 Bootsel Pin & Signal Descriptions for the PXA255 Processor Sheet 8Rtcclk Icocz PwrenPin Description Notes Sheet 1 Pin & Signal Descriptions for the PXA255 Processor Sheet 9Pin Description Notes Sheet 2 Memory MapMemory Map Part One From 0x80000000 to 0xFFFF Ffff Memory Map Part Two From 0x00000000 to 0x7FFF Ffff Unit Address Register Symbol Register Description System Architecture Register SummarySystem Architecture Register Address Summary Sheet 1 System Architecture Register Address Summary Sheet 2 System Architecture Register Address Summary Sheet 3 System Architecture Register Address Summary Sheet 4 Unit System Architecture Register Address Summary Sheet 5System Architecture Register Address Summary Sheet 6 Unit Address System Architecture Register Address Summary Sheet 7System Architecture Register Address Summary Sheet 8 System Architecture Register Address Summary Sheet 9 System Architecture Register Address Summary Sheet 10 System Architecture Register Address Summary Sheet 11 System Architecture Register Address Summary Sheet 12 Clock Manager Introduction Clocks and Power ManagerClock Manager Power Manager IntroductionPWM SSP Retains Power in SleepOST Ficp I2C MMCCore Phase Locked Loop 1 32.768 kHz Oscillator2 3.6864 MHz Oscillator 5 147.46 MHz Peripheral Phase Locked Loop 4 95.85 MHz Peripheral Phase Locked LoopCore PLL Output Frequencies for 3.6864 MHz Crystal SdramResets and Power Modes Hardware ResetClock Gating Watchdog Reset Completing a Watchdog Reset Gpio ResetInvoking Gpio Reset Behavior During Gpio ResetTurbo Mode Run ModeCompleting Gpio Reset Entering Turbo ModeBehavior in Turbo Mode Idle ModeExiting Turbo Mode Entering Idle ModeExiting Idle Mode Behavior in Idle ModeFrequency Change Sequence Preparing for a Frequency Change SequenceBehavior During the Frequency Change Sequence Invoking the Frequency Change SequenceCompleting the Frequency Change Sequence 8 33-MHz Idle ModeBehavior in 33-MHz Idle Mode Entering 33-MHz Idle ModeSleep Mode Exiting 33-MHz Idle ModeSleep Mode External Voltage Regulator Requirements Entering Sleep Mode Preparing for Sleep ModeClocks and Power Manager Exiting Sleep Mode Behavior in Sleep ModeClocks and Power Manager Power Mode Entry Sequence Table Power Mode SummaryPower Mode Exit Sequence Table Sheet 1 IdlePower Mode Exit Sequence Table Sheet 2 Power Mode Supply Source Module Turbo Run Power Manager RegistersPmcr Bit Definitions Power Manager Control Register PmcrPmcr IdaePcfr Bit Definitions Power Manager General Configuration Register PcfrPcfr OpdePwer Bit Definitions Power Manager Wake-Up Enable Register PwerWertc Pwer10. Prer Bit Definitions Power Manager Rising-Edge Detect Enable Register Prer0x40F00010 Prer11. Pfer Bit Definitions Power Manager Falling-Edge Detect Enable Register Pfer0x40F00014 Pfer12. Pedr Bit Definitions Power Manager Gpio Edge Detect Status Register Pedr0x40F00018 Pedr13. Pssr Bit Definitions Sheet 1 Power Manager Sleep Status Register PssrPssr RDH13. Pssr Bit Definitions Sheet 2 Power Manager Scratch Pad Register Pspr14. Pspr Bit Definitions CPU VFS15. Pmfw Register Bitmap and Bit Definitions Power Manager Fast Sleep Walk-up Configuration Register Pmfw17. PGSR1 Bit Definitions 16. PGSR0 Bit DefinitionsPGSR0 SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0Bit Reset 0x40F00028 Reset Controller Status Register Rcsr18. PGSR2 Bit Definitions PGSR2Clocks Manager Registers Core Clock Configuration Register Cccr19. Rcsr Bit Definitions Rcsr0x41300000 20. Cccr Bit DefinitionsBit Reserved Multiplier =21. Cken Bit Definitions Sheet 1 Clock Enable Register Cken21. Cken Bit Definitions Sheet 2 Description I2S Unit Clock EnableCKEN8 CKEN5Coprocessor 14 Clock and Power Management Oscillator Configuration Register Oscc22. Oscc Bit Definitions Core Clock Configuration Register Cclkcfg 23. Coprocessor 14 Clock and Power Management Summary24. Cclkcfg Bit Definitions Power-On-Reset Considerations Power Mode Register PwrmodePower Supply Connectivity External Hardware ConsiderationsDriving the Crystal Pins from an External Clock Source Clocks and Power Manager Register SummaryPower Manager Register Summary Clocks Manager Register Locations27. Power Manager Register Summary Gpio Operation General-Purpose I/OGpio Alternate Functions General-Purpose I/O Block DiagramGpio Alternate Functions Sheet 1 Gpio Alternate Functions Sheet 2 Gpio Alternate Functions Sheet 3 MMCCS0 ALTFN1OUTMbgnt ALTFN1OUT Gpio Register Definitions Gpio Alternate Functions Sheet 4Gpio Register Definitions Sheet 1 Gpio Register Definitions Sheet 2 Gpio Pin-Level Registers GPLR0, GPLR1, GPLR2GPLR0 Bit Definitions GPLR0GPLR1 Bit Definitions Gpio Pin Direction Registers GPDR0, GPDR1, GPDR2GPLR2 Bit Definitions GPLR1GPDR0 Bit Definitions GPDR1 Bit DefinitionsGPDR2 Bit Definitions 10. GPSR1 Bit Definitions GPSR0 Bit DefinitionsGPSR0 PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS011. GPSR2 Bit Definitions 12. GPCR0 Bit Definitions13. GPCR1 Bit Definitions GPCR2 GPCR2 Bit Definitions15. GRER0 Bit Definitions 16. GRER1 Bit Definitions17. GRER2 Bit Definitions 18. GFER0 Bit Definitions 19. GFER1 Bit DefinitionsGFER2 Bit Definitions Gpio Edge Detect Status Register GEDR0, GEDR1, GEDR2 21. GEDR0 Bit Definitions22. GEDR1 Bit Definitions GEDR2 GEDR2 Bit Definitions25. GAFR0U Bit Definitions 24. GAFR0L Bit DefinitionsGAFR0L AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF027. GAFR1U Bit Definitions 26. GAFR1L Bit DefinitionsGAFR1L GAFR1U29. GAFR2U Bit Definitions 28. GAFR2L Bit DefinitionsGAFR2L GAFR2UInterrupt Controller Operation Interrupt ControllerInterrupt Controller Register Definitions Interrupt Controller Block DiagramInterrupt Controller Level Register Iclr Interrupt Controller Mask Register Icmr30. Icmr Bit Definitions IcmrInterrupt Controller Control Register Iccr 31. Iclr Bit Definitions32. Iccr Bit Definitions 34. Icfp Bit Definitions 33. Icip Bit Definitions35. Icpr Bit Definitions Sheet 1 Interrupt Controller Pending Register IcprIcpr IS9 IS835. Icpr Bit Definitions Sheet 2 Network SSP Service Request Interrupt PendingIS14 IS13 IS12 IS11 IS10 IS1636. List of First-Level Interrupts Sheet 1 35. Icpr Bit Definitions Sheet 3System Integration Unit Bit Position Source UnitReal-Time Clock RTC Real-Time Clock Operation36. List of First-Level Interrupts Sheet 2 RTC Trim Register Rttr RTC Register DefinitionsRTC Alarm Register Rtar Rttr Bit Definitions38. Rtar Bit Definitions RTC Status Register Rtsr RTC Counter Register Rcnr39. Rcnr Bit Definitions RcnrTrim Procedure Oscillator Frequency Calibration40. Rtsr Bit Definitions Rttr Value Calculations Trim Example #1 Measured Value Has No Fractional ComponentTrim Example #2 Measured Value Has a Fractional Component Maximum Error Calculation Versus RTC Accuracy Operating System OS TimerWatchdog Timer Operation OS Timer Register DefinitionsOS Timer Match Register 0-3 OSMRx 41. OSMRx Bit Definitions OS Timer Interrupt Enable Register Oier42. Oier Bit Definitions OSMR3, OSMR2, OSMR1OS Timer Count Register Oscr OS Timer Watchdog Match Enable Register OwerOS Timer Status Register Ossr 43. Ower Bit DefinitionsPulse Width Modulator 0x40A00014 Bit Reset ? ? ? ? ? ? ? ? BitsPulse Width Modulator Operation Ossr Bit Definitions1.1 Interdependencies PWMn Block DiagramPower Management Requirements Reset SequenceRegister Descriptions PWM Control Registers PWMCTRLn46. PWMCTRLn Bit Definitions PWM Duty Cycle Registers PWMDUTYn0x40B00000 Prescale47. PWMDUTYn Bit Definitions PWM Period Control Register PWMPERVALnPWMDUTY0, PWMDUTY1 Fdcycle DcyclePulse Width Modulator Output Wave Example 48. PWMPERVALn Bit Definitions0x40B00008 System Integration Unit Register Summary Gpio Register Locations49. Gpio Register Addresses Sheet 1 OS Timer Register Locations Interrupt Controller Register LocationsReal-Time Clock Register Locations 52. OS Timer Register Addresses Sheet 2 Pulse Width Modulator Register Locations53. Pulse Width Modulator Register Addresses DMA Description Dmac Block DiagramDREQ10 and PREQ370 Signals Signal DescriptionsDmac Signal List Signal Signal Type To/From Definition In/OutDMA Channel Priority Scheme Dmairq SignalChannel Priority Channel Priority if all channels are running concurrentlyDMA Descriptors No-Descriptor Fetch ModePriority Schemes Examples DMA Channel PriorityNo-Descriptor Fetch Mode Channel State Descriptor Fetch ModeDMA Controller Servicing an Interrupt Channel StatesByte Transfer Order Read and Write OrderLittle Endian Transfers Trailing BytesServicing Internal Peripherals Transferring DataDcmdincsrcaddr = Dcmdflowsrc = Dcmdflowtrg = DMA Quick Reference for Internal Peripherals Sheet 1 Quick Reference for DMA ProgrammingDcmd DrcmrDMA Quick Reference for Internal Peripherals Sheet 2 Servicing Companion Chips and External PeripheralsUnit Function Fifo Address Width Burst Size SourceDMA Controller Memory-to-Memory Moves DMA Interrupt Register Dint Dmac RegistersDMA Channel Control/Status Register DCSRx Dint Bit DefinitionsRUN DCSRx Bit Definitions Sheet 1Reqpend Stopstate Endintr Startintr BuserrintrDCSRx Bit Definitions Sheet 2 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMA Descriptor Address Registers DDADRx DMA Request to Channel Map Registers DRCMRxDRCMRx Bit Definitions ChlnumDDADRx Bit Definitions DMA Source Address RegistersDescriptor Address Stop10. DSADRx Bit Definitions DMA Target Address Registers DTADRxSource Address Srcaddr11. DTADRx Bit Definitions DMA Command Registers DCMDxTarget Address TrgaddrIncsrcaddr 12. DCMDx Bit Definitions Sheet 1Endian Width SizeEndian 12. DCMDx Bit Definitions Sheet 2Width LengthExamples Example 1. How to set up and start a channelStruct longddadr longdsadr longdtadr shortlength shortdcmd 13. DMA Controller Register Summary Sheet 1 DMA Controller Register Summary13. DMA Controller Register Summary Sheet 2 13. DMA Controller Register Summary Sheet 3 13. DMA Controller Register Summary Sheet 4 13. DMA Controller Register Summary Sheet 5 Memory Controller Sdram Interface Overview Functional DescriptionStatic Memory Interface / Variable Latency I/O Interface 3 16-Bit PC Card / Compact Flash Interface Memory System ExamplesSdram Memory System Example Static Memory System Example Device Transactions Memory AccessesBus Operation Burst Size Words BitsReads and Writes Synchronous Dram Memory InterfaceAborts and Nonexistent Memory Sdram Mdcnfg Register MdcnfgMdcnfg Bit Definitions Sheet 1 Mdcnfg Bit Definitions Sheet 2 DNB2 Mdcnfg Bit Definitions Sheet 3DADDR2 DLATCH2Mdmrs Bit Definitions Sheet 1 Sdram Mode Register Set Configuration Register MdmrsMdmrs Bit Definitions Sheet 2 Low-Power Sdram Mode Register Set Configuration RegisterMdmrslp Register Bit Definitions Sdram Mdrefr Register Mdrefr0X4800 MdmrslpMdrefr Mdrefr Bit Definitions Sheet 1APD K2DB2 K2RUN K1DB2 K1RUN E1PIN K0DB2 K0RUN E0PIN DRIMdrefr Bit Definitions Sheet 2 0 1 0 0 1 * * 11 1 1 1 1 1 1 Fixed-Delay or Return-Clock Data Latching Mdrefr Bit Definitions Sheet 3APD Sdram Addressing Modes Sdram Memory OptionsSample Sdram Memory Size Options Number Chips Partition Size# Bits ‘0’1x12x8x32 ‘0’ 1x12x8x16 1x12x9x32 1x12x9x16 1x12x10x32 Col Data MA24102x13x10x16 ‘0’ Not Valid illegal addressing combination # Bits External Address pins at Sdram RAS TimeMA20 MA24 MA23BA0 A10BA1 BA0 MA24A11 A10 Memory Controller A12 Sdram Command Overview11. Sdram Command Encoding 12. Sdram Mode Register Opcode TableSdram Waveforms Data SdclkSDRAMreadsamebankdiffrow SDCLK1 SDCKE1 SDRAMwriteSynchronous Static Memory Interface Synchronous Static Memory Configuration Register Sxcnfg0x4800001C 13. Sxcnfg Bit Definitions Sheet 1Sxcnfg SXLATCH2 SXTP2 SXCA2 SXRA2 SXRL2 SXCL2 SXEN2SXLATCH2 Sxcnfg Bit Definitions Sheet 2SXRL2 SXCL2 SXEN2 SXLATCH013. Sxcnfg Bit Definitions Sheet 3 Sxcnfg Bit Definitions Sheet 4 Smrom Memory OptionsSXCL0 SXEN0Smrom 16. Sxmrs Bit Definitions Synchronous Static Memory Timing DiagramsSxmrs SXMRS2Sdclk Sdcke Non-SDRAM Timing Sxmem OperationMemclk SDCLK0 Mdrefr 17. Read Configuration Register Programming Values12shows the burst-of-eight read timing diagram Non-SDRAM Timing Flash Read Timing Diagram4.2 K3 Synchronous StrataFlash Reset Asynchronous Static MemoryStatic Memory Interface Sram 20 -Bit Bus Write Access 19 -Bit Bus Write AccessData Size MA10 DQM30 Data Size MA0 DQM1021 -Bit Byte Address Bits MA10 for Reads Based on DQM30 22 -Bit Byte Address Bit MA0 for Reads Based on DQM1023. SA-1111 Register Bit Definitions Asynchronous Static Memory Control Registers MSCx MSC0 24. MSC0/1/2 Bit Definitions Sheet 1MSC1 MSC2RRR1/3/5 RDN1/3/5 Reset RDF1/3/5 Bits Access Name24. MSC0/1/2 Bit Definitions Sheet 2 Sram 24. MSC0/1/2 Bit Definitions Sheet 3Timing Memory Clocks MSCxRTx Device ROM InterfaceNOE NWE NOEClkmem ROM Timing Diagrams and ParametersRDN+1 Sram Interface Overview Sram Timing Diagrams and Parameters20shows the timing for Sram writes Variable Latency I/O Vlio Interface Overview RDF+1+Waits RRR*2+1 Variable Latency I/O Timing Diagrams and ParametersRDF+1+Waits Flash Memory Interface Flash Memory Timing Diagrams and ParametersCMD Data 23. Asynchronous 32-Bit Flash Write Timing Diagram 2 Writes16-Bit PC Card/Compact Flash Interface Expansion Memory Timing Configuration Register26. MCMEM0/1 Bit Definitions MCMEM028. MCIO0/1 Bit Definitions 27. MCATT0/1 Bit DefinitionsMCATT0 MCATT1MCMEMxASST XASSTHOLD XASSTWAIT + 29. Card Interface Command Assertion Code Table30. Mecr Bit Definition Expansion Memory Configuration Register MecrMecr CIT NOS26 -Bit PC Card Memory Map 3 16-Bit PC Card Overview32. Common Memory Space Read Commands 31. Common Memory Space Write Commands33. Attribute Memory Space Write Commands 34. Attribute Memory Space Read Commands37 -Bit I/O Space Write Commands nIOIS16 = 38 -Bit I/O Space Read Commands nIOIS16 =External Logic for 16-Bit PC Card Implementation DIR Socket 29 -Bit PC Card Memory or I/O 16-Bit Half-word Access Expansion Card Interface Timing Diagrams and ParametersCompanion Chip Interface 30 -Bit PC Card I/O 16-Bit Access to 8-Bit Device32. Variable Latency IO 31. Alternate Bus Master ModeAlternate Bus Master Mode Gpio Reset NVDDFAULT/nBATTFAULT with Pmcridae DisabledNVDDFAULT/nBATTFAULT with Pmcridae Enabled Alternate Booting Options and Settings for Boot MemoryBoot Time Defaults Bootdef Read-Only Register Bootdef41. Valid Boot Configurations Based on Processor Type 40. Bootdef BitmapBootdef PKG Type Boot SELSxcnfg Boot-Time Configurations34. Smrom Boot Time Configurations and Register Defaults Memory Interface Reset and Initialization SmromMdrefr 03CA 7FFF Hardware, Watchdog, or Sleep Reset Operation 42. Memory Controller Pin Reset ValuesPin Name PXA255 Processor Reset Value Memory Controller Physical Address Symbol Register Name Gpio Reset ProcedureMemory Controller Register Summary 43. Memory Controller Register Summary Sheet 143. Memory Controller Register Summary Sheet 2 LCD Controller LCD Controller FeaturesLCD Controller Block Diagram Pin Descriptions LCD Controller OperationEnabling the Controller Pin DescriptionsDetailed Module Descriptions Resetting the ControllerDisabling the Controller Input FIFOsTemporal Modulated Energy Distribution Tmed Dithering Lookup PaletteCompare Range for Tmed LCD Controller Pin Usage Output FIFOs6 DMA Pixel Data Pins LDDxPassive Display Timing Active Display TimingExternal Palette Buffer LCD External Palette and Frame BuffersPalette Buffer Format External Frame BufferBits Per Pixel Data Memory Organization 10 Bits Per Pixel Data Memory Organization Passive Mode FrameBufferSize = Functional Timing12. Passive Mode Start-of-Frame Timing Hsync Lbias VsyncLfclk Vsync Llclk Hsync Lbias Register DescriptionsLCD Controller Control Register 0 LCCR0 LCD Controller LDD LCD Controller Data Pin Utilization Sheet 1 LCD Controller Data Pin Utilization Sheet 2 Single Passive Screen Portion PinsLCCR0 Bit Definitions Sheet 1 Reset X X X X X X X X X X XLCCR0 0x44000000 Bit ReservedLCCR0 Bit Definitions Sheet 2 LCD Controller Control Register 1 LCCR1QDM DIS DPD PAS EFM IUM SFM LDM SDS CMS ENBLCD Controller LCCR1 Bit Definitions LCD Controller Control Register 2 LCCR2BLW ELW HSW PPL BLWLCD Controller LCCR2 Bit Definitions LCD Controller Control Register 3 LCCR3BFW EFW VSW LPP BFWLCD Controller LCD Controller LCCR3 Bit Definitions Sheet 1 Reset X X X X 0 0 00x4400000C Bit Reserved DPC BPPLCD Controller DMA Reset X X XFrame Descriptors LCCR3 Bit Definitions Sheet 2LCD DMA Frame Source Address Registers FSADRx LCD DMA Frame Descriptor Address Registers FDADRxFDADRx Bit Definitions FDADR0LCD DMA Frame ID Registers FIDRx FSADRx Bit DefinitionsFIDRx Bit Definitions LCD DMA Command Registers LDCMDx LDCMD0 10. LDCMDx Bit DefinitionsLDCMD1 PAL11. FBRx Bit Definitions LCD DMA Frame Branch Registers FBRxBint BRA 0 0 0 0 X X 0 Bits Name DescriptionLCD Controller Status Register Lcsr LCD Controller Lcsr Bit Definitions Sheet 1 0x44000038 Bit Reset X XX X EOF IUU IUL ABC BER SOF LDD12. Lcsr Bit Definitions Sheet 2 LCD Controller Interrupt ID Register Liidr13. Liicr Bit Definitions Sint BS EOF QD OU IUU IUL ABC BER SOF LDD14. Trgbr Bit Definitions Tmed RGB Seed Register TrgbrTBS TRSTmed Control Register TCR LCD Controller Register Summary 15. TCR Bit Definitions16. LCD Controller Register Summary Sheet 1 16. LCD Controller Register Summary Sheet 2 LCD Controller External Interface to Synchronous Serial Peripherals Signal DescriptionExternal Interface to Codec Name Direction DescriptionData Formats Data TransferSerial Data Formats for Transfer to/from Peripherals SSP Format Details Sspsclk Sspsfrm SPI Format DetailsSspsclk Sspsfrm MSB LSBSspsclk Sspsfrm Ssptxd Ssprxd Microwire Format DetailsParallel Data Formats for Fifo Storage National Microwire* Frame FormatUsing DMA Data Transfers Using Programmed I/O Data TransfersFifo Operation and Data Transfers Baud-Rate GenerationSSP Control Register 0 SSCR0 SSP Serial Port RegistersSSCR0 Bit Definitions Data Size Select DSSSSP Control Register 0 SSCR0 SCRSynchronous Serial Port Enable SSE Frame Format FRFExternal Clock Select ECS SSP Control Register 1 SSCR1 Serial Clock Rate SCRSSCR1 Bit Definitions Sheet 1 Transmit Fifo Interrupt Enable TIE Receive Fifo Interrupt Enable RIELoop Back Mode LBM SSCR1 Bit Definitions Sheet 2Serial Clock Phase SPH Serial Clock Polarity SPOSspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd Transmit Fifo Interrupt/DMA Threshold TFT Microwire Transmit Data Size MwdsReceive Fifo Interrupt/DMA Threshold RFT Ssprxd Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm SsptxdSSP Data Register Ssdr TFT and RFT Values for DMA ServicingSsdr Bit Definitions SSP Status Register Sssr Sssr Bit Definitions Transmit Fifo Not Full Flag TNFRFL TFL ROR RFS TFS BSY RNE TNF RFLReceive Fifo Service Request Flag RFS Transmit Fifo Service Request Flag TFSReceive Fifo Not Empty Flag RNE SSP Busy Flag BSYReceive Fifo Level RFL SSP Controller Register SummarySSP Controller Register Summary Address Abbreviation Full NameSynchronous Serial Port Controller Signal Name Input/Output Description I2C Signal DescriptionSDA SCL2C Device Definition I2C Bus DefinitionsOperational Blocks Mode Description2 I2C Bus Interface Modes Modes of OperationStart and Stop Bit Definitions Start and Stop Bus StatesStop Star ConditionStart Condition No Start or Stop ConditionStop Condition Start ACK NAKACK ACK Stop NAKI2C Bus Operation Serial Clock Line SCL GenerationData and Addressing Management Addressing a Slave Device 3 I2C AcknowledgeArbitration PollingSDA Arbitration SCL ArbitrationArbitration Procedure of Two Masters 2C Master Mode Definition Action Operation Master OperationsMaster Transactions Sheet 1 Master Transactions Sheet 2 Master-Receiver Read from Slave-Transmitter Slave OperationsSlave Transactions 2C Slave Action Mode Definition OperationGeneral Call Address ACK StopNAK Stop Least Second General Call Address Second Byte DefinitionsInitialize Unit Slave Mode Programming ExamplesWrite n Bytes as a Slave Read n Bytes as a SlaveWrite 1 Byte as a Master Master Programming ExamplesWrite 2 Bytes and Repeated Start Read 1 Byte as a Master Read 1 Byte as a MasterReset Conditions Read 2 Bytes as a Master Send Stop Using the AbortGlitch Suppression Logic 1 I2C Bus Monitor Register Ibmr Register Definitions2 I2C Data Buffer Register Idbr Ibmr Bit Definitions3 I2C Control Register ICR Idbr Bit Definitions10. ICR Bit Definitions Sheet 1 Disable interrupt 40301690 Bit Reset10. ICR Bit Definitions Sheet 2 Beie Irfie Iteie GCD IUEReceive mode 4 I2C Status Register ISR10. ICR Bit Definitions Sheet 3 2C Status Register 11. ISR Bit Definitions Sheet 140301698 Bit BED SAD11. ISR Bit Definitions Sheet 2 5 I2C Slave Address Register Isar12. Isar Bit Definitions BED SAD Gcad IRF ITE ALD SSD IBBI2C Bus Interface Unit UARTs Feature ListFull Function Uart Bluetooth UartStandard Uart Compatibility withUart Signal Descriptions Sheet 1 Signal DescriptionsName Type Description RXDUart Signal Descriptions Sheet 2 Uart Operational DescriptionLSB MSB Internal Register Descriptions ResetReceive Buffer Register RBR Register AccessedUart Register Addresses as Offsets of a Base RBR Bit DefinitionsTransmit Holding Register THR Divisor Latch Registers DLL and DLHTHR Bit Definitions Interrupt Enable Register IER DLL Bit DefinitionsDLH Bit Definitions IER Bit Definitions Interrupt Identification Register IIRIIR Bit Definitions Sheet 1 Interrupt ConditionsPriority Level Interrupt origin FIFOES10Fcrresetrf Interrupt ID Bits Interrupt SET/RESET FunctionIIR Bit Definitions Sheet 2 10. Interrupt Identification Register Decode Sheet 110. Interrupt Identification Register Decode Sheet 2 Fifo Control Register FCR11. FCR Bit Definitions Sheet 1 ITL11. FCR Bit Definitions Sheet 2 Line Control Register LCR12. LCR Bit Definitions Base+0x0CUart Dlab Stkyp EPS PEN STB WLS1 WLS0 13. LSR Bit Definitions Sheet 1 Line Status Register LSRFifoe TemtTdrq 13. LSR Bit Definitions Sheet 213. LSR Bit Definitions Sheet 3 14. MCR Bit Definitions Sheet 1 Modem Control Register MCRUart Loop OUT2 OUT1 RTS DTRModem Status Register MSR 14. MCR Bit Definitions Sheet 2Base+0x10 Modem Control Register 15. MSR Bit Definitions Character Timeout Indication Interrupt Fifo Interrupt Mode OperationScratchpad Register SPR Receive InterruptFifo Polled Mode Operation DMA RequestsTransmit Interrupt Slow Infrared Asynchronous Interface Trailing Bytes in the Receive FifoInfrared Selection Register ISR 17. ISR Bit Definitions OperationIR Transmit and Receive Example 18. Ffuart Register Summary Uart Register Summary19. Btuart Register Summary Sheet 1 Dlab Bit Name Description20. Stuart Register Summary 19. Btuart Register Summary Sheet 221. Flow Control Registers in Btuart and Stuart Uart Register DifferencesBtmcr BtmsrFicp Operation Ficp Signal DescriptionPPM Modulation Encodings 11.2.1 4PPM ModulationAddress Field Frame FormatControl Field Data FieldCRC Field Baud Rate GenerationReceive Operation Transmit Operation Transmit and Receive FIFOs Ficp Register Definitions Trailing or Error Bytes in the Receive FifoICCR0 Bit Definitions Sheet 1 Ficp Control Register 0 ICCR0TXE ICCR0 Bit Definitions Sheet 2TUS LBMICCR1 Bit Definitions Ficp Control Register 1 ICCR1ICCR2 Bit Definitions Ficp Control Register 2 ICCR2Icrd Bit Definitions Ficp Data Register IcdrICSR0 Bit Definitions Sheet 1 Ficp Status Register 0 ICSR0FRE RFSICSR0 Bit Definitions Sheet 2 TUREIF ICSR1 Bit Definitions Ficp Status Register 1 ICSR1Ficp Register Summary Ficp Register SummaryUSB Overview USB Device ControllerEndpoint Configuration Device ConfigurationUSB Protocol IN/OUTBit Encoding Signalling LevelsUSB States Bus State UDC+/UDC- Pin LevelsNrzi Bit Encoding Example Field FormatsPacket Formats IN, OUT, and Setup Token Packet FormatToken Packet Type Start of Frame Packet TypeData Packet Type Transaction FormatsHandshake Packet Type Bulk Transaction TypeControl Transaction Type Isochronous Transaction TypeBulk Transaction Formats Isochronous Transaction FormatsUDC Device Requests Interrupt Transaction Type10. Interrupt Transaction Formats Configuration 11. Host Device Request SummaryRequest Name UDC Hardware Connection Self-Powered DeviceWhen GPIOn and GPIOx are the Same Pin When GPIOn and GPIOx are Different PinsBus-Powered Devices UDC OperationCase 1 EP0 Control Read Case 2 EP0 Control Read with a Premature Status Stage 12-14 Intel PXA255 Processor Developer’s Manual Case 4 EP0 No Data Command Software Enables the DMACase 5 EP1 Data Transmit BULK-IN Case 6 EP2 Data Receive BULK-OUT Software Enables the EP1 InterruptSoftware Enables DMA Case 7 EP3 Data Transmit ISOCHRONOUS-INSoftware Allows the Megacell to Handle the Transaction Software Enables the EP3 Interrupt Software Enables the SOF InterruptCase 8 EP4 Data Receive ISOCHRONOUS-OUT Intel PXA255 Processor Developer’s Manual 12-19 Case 9 EP5 Data Transmit INTERRUPT-IN Case 10 Reset InterruptUDC Register Definitions Case 11 Suspend InterruptCase 12 Resume Interrupt UDC Enable UDE UDC Control Register Udccr12. Udccr Bit Definitions Reset Interrupt Mask REM Reset Interrupt Request RstirUDC Active UDA UDC Resume RSMACK Response Enable ACK Control ModeUDC Control Function Register Udccfr 13. UDC Control Function RegisterOUT Packet Ready OPR UDC Endpoint 0 Control/Status Register UDCCS0Packet Ready IPR 14. UDCCS0 Bit DefinitionsFlush Tx Fifo FTF Device Remote Wakeup Feature DrwfSent Stall SST Force Stall FSTTransmit Fifo Service TFS Setup Active SAUDC Endpoint x Control/Status Register UDCCS1/6/11 15. UDCCS1/6/11 Bit DefinitionsTransmit Packet Complete TPC Transmit Underrun TURBit 6 Reserved UDC Endpoint x Control/Status Register UDCCS2/7/12 Transmit Short Packet TSP16. UDCCS2/7/12 Bit Definitions DMA Enable DME Receive Fifo Service RFSReceive Packet Complete RPC Bit 2 ReservedUDC Endpoint x Control/Status Register UDCCS3/8/13 Receive Short Packet RSP17. UDCCS3/8/13 Bit Definitions Bits 64 Reserved UDC Endpoint x Control/Status Register UDCCS4/9/1418. UDCCS4/9/14 Bit Definitions Receive Overflow ROFUDC Endpoint x Control/Status Register UDCCS5/10/15 Bits 54 Reserved19. UDCCS5/10/15 Bit Definitions Sheet 1 19. UDCCS5/10/15 Bit Definitions Sheet 2 UDC Interrupt Control Register 0 UICR0 20. UICR0 Bit Definitions Interrupt Mask Endpoint x IMx, Where x is 0 throughUICR0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0UDC Interrupt Control Register 1 UICR1 Interrupt Mask Endpoint x IMx, where x is 8 through21. UICR1 Bit Definitions UICR1Endpoint 0 Interrupt Request IR0 UDC Status/Interrupt Register 0 USIR0Endpoint 1 Interrupt Request IR1 22. USIR0 Bit DefinitionsEndpoint 3 Interrupt Request IR3 Endpoint 2 Interrupt Request IR2Endpoint 4 Interrupt Request IR4 Endpoint 5 Interrupt Request IR5Endpoint 8 Interrupt Request IR8 UDC Status/Interrupt Register 1 USIR1Endpoint 9 Interrupt Request IR9 Endpoint 10 Interrupt Request IR10UDC Frame Number High Register Ufnhr Isochronous Packet Error Endpoint 9 IPE9 Isochronous Packet Error Endpoint 4 IPE4UDC Frame Number MSB Fnmsb 24. Ufnhr Bit DefinitionsUDC Frame Number Low Register Ufnlr Isochronous Packet Error Endpoint 14 IPE14UDC Byte Count Register x UBCR2/4/7/9/12/14 Start of Frame Interrupt Mask SIMUDC Endpoint 0 Data Register UDDR0 Endpoint x Byte Count BC26. UBCR2/4/7/9/12/14 Bit Definitions UDC Endpoint x Data Register UDDR2/7/12 UDC Endpoint x Data Register UDDR1/6/1127. UDDR0 Bit Definitions 28. UDDR1/6/11 Bit DefinitionsUDC Endpoint x Data Register UDDR4/9/14 UDC Endpoint x Data Register UDDR3/8/1329. UDDR2/7/12 Bit Definitions 30. UDDR3/8/13 Bit DefinitionsUDC Endpoint x Data Register UDDR5/10/15 USB Device Controller Register Summary31. UDDR4/9/14 Bit Definitions 32. UDDR5/10/15 Bit Definitions33. USB Device Controller Register Summary Sheet 2 UfnhrUfnlr 33. USB Device Controller Register Summary Sheet 3 AC’97 Controller Unit Example AC-link Signal Configuration StepsExternal Interface to CODECs Name Direction Description summarySupported Data Stream Formats Sheet 1 AC-link Digital Serial Interface ProtocolSDATAIN0 SDATAIN1 Channel Slots CommentsAC-link Audio Output Frame Sdataout Supported Data Stream Formats Sheet 2Sync AC-link Audio Output Frame Slot 1 Command Address Port Slot 0 Tag PhaseSlot 3 PCM Playback Left Channel Slot 2 Command Data PortSlot 1 Bit Definitions Slot 2 Bit DefinitionsSlot 4 PCM Playback Right Channel AC-link Audio Input Frame SdatainSlot 5 Modem Line Codec Slots 6-11 ReservedSync Slot 1 Status Address Port/SLOTREQ bits Input Slot 1 Bit Definitions Sheet 1Bit Description Slot 3 PCM Record Left Channel Slot 2 Status Data PortSlot 4 PCM Record Right Channel Slot 5 Optional Modem Line CodecPowering Down the AC-link AC-link Low Power ModeSlots 7-11 Reserved Slot 12 I/O StatusWake up triggered by the Codec Waking up the AC-linkWarm AC’97 Reset Cold AC’97 ResetAcunit Operation Wake Up Triggered by the AcunitInitialization 13-16 Intel PXA255 Processor Developer’s Manual Clocks and Sampling Frequencies Operational Flow for Accessing Codec RegistersTransmit Fifo Errors Receive Fifo ErrorsFIFOs Registers InterruptsGCR Bit Definitions Sheet 1 Global Control Register GCRGCR Bit Definitions Sheet 2 Global Status Register GSRWarmrst ColdrstCdone Sdone GSR Bit Definitions Sheet 1Rdcs Secres Prires SCR PCR Mint Point PiintPCM-Out Control Register Pocr GSR Bit Definitions Sheet 2Pocr Bit Definitions Sheet 1 PCM-In Control Register Picr Pocr Bit Definitions Sheet 210. Picr Bit Definitions PCMIn Status Register Pisr PCM-Out Status Register Posr11. Posr Bit Definitions 12. Pisr Bit DefinitionsPCM Data Register Pcdr Codec Access Register CAR13. CAR Bit Definitions 14. Pcdr Bit DefinitionsMic-In Status Register Mcsr Mic-In Control Register Mccr15. Mccr Bit Definitions Mccr Register16. Mcsr Bit Definitions Mic-In Data Register Mcdr17. Mcdr Bit Definitions MicindatModem-In Control Register Micr Modem-Out Control Register Mocr18. Mocr Bit Definitions Mocr RegisterModem-In Status Register Misr Modem-Out Status Register Mosr19. Micr Bit Definitions 20. Mosr Bit Definitions21. Misr Bit Definitions Modem Data Register Modr22. Modr Bit Definitions Modemdat11. Modem Transmit and Receive Operation Accessing Codec Registers23. Address Mapping for Codec Registers Sheet 1 Processor Bit PhysicalAddress for a Primary Secondary Audio Codec Modem Codec 23. Address Mapping for Codec Registers Sheet 2 24. Register Mapping Summary 13.9 AC’97 Register Summary13-36 Intel PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound I2S Controller GP29/SDATAIN GP32/SYSCLKController Operation Disabling and Enabling Audio Record Disabling and Enabling Audio ReplayTransmit Fifo Errors Receive Fifo ErrorsSerial Audio Clocks and Sampling Frequencies 14.5.2 I2S and MSB-Justified Serial Audio Formats Fifo and Memory FormatSupported Sampling Frequencies Sysclk = Bitclk =I2S Data Formats 16 bits Serial Audio Controller Global Control Register SACR0 RegistersSACR0 Bit Definitions Special purpose Fifo Read/Write functionFifo Write/Read table Suggested Tfth and Rfth for DMA servicingTfth and Rfth Values for DMA Servicing Efwr StrfEnlbf SACR1 Bit DefinitionsDrpl DrecSASR0 Bit Definitions Serial Audio Clock Divider Register SadivRFL TFLSerial Audio Interrupt Clear Register Saicr Sadiv Bit DefinitionsSaicr Bit Definitions Serial Audio Data Register Sadr Serial Audio Interrupt Mask Register Saimr10. Saimr Bit Descriptions 11. Sadr Bit Descriptions14.8 I2S Controller Register Summary Transmit and Receive Fifo Accesses Through the SadrAddress Register Description Paddr90 Name 12. Register Memory MapMultiMediaCard Controller Command Token Format MMC Data Token FormatSPI Data Token Format Mmdat MmcmdCRC MMC Controller Functional DescriptionIntel PXA255 Processor Developer’s Manual 15-5 MMC Controller Reset Signal DescriptionMMC Signal Description Card Initialization SequenceMMC Mode SPI Mode Error DetectionClock Control Data FIFOs Response Data Fifo MmcresReceive Data FIFO, Mmcrxfifo Transmit Data FIFO, Mmctxfifo DMA and Program I/O Card Communication ProtocolMmcclkrt Mmcspi Mmcresto Basic, No Data, Command and Response SequenceBlock Data Write Stream Data Write Block Data ReadStream Data Read Busy SequenceMultiMediaCard Controller Operation Enabling SPI ModeSPI Functionality Start and Stop ClockNo Data Command and Response Sequence EraseSingle Data Block Write Single Block Read Multiple Block Read Multiple Block WriteStream Read Stream WriteMmcstrpcl Register MMC Controller RegistersMmcstrpcl Bit Definitions MMCStatus Register MmcstatMmcstat Bit Definitions Sheet 1 StrpclMmcstat Bit Definitions Sheet 2 Mmcclkrt Register MmcclkrtMmcspi Register Mmcspi Mmcclk Bit DefinitionsMmcspi Bit Definitions Sheet 1 Mmccmdat Register Mmccmdat Mmcspi Bit Definitions Sheet 2Mmccmdat Bit Definitions Sheet 1 Mmcresto Register Mmcresto Mmccmdat Bit Definitions Sheet 210. Mmcresto Bit Definitions 11. Mmcrdto Register Mmcrdto Register MmcrdtoReadto Specifies the length of time before a data read time-outMmcnob Register Mmcnob Mmcblklen Register Mmcblklen12. Mmcblklen Bit Definitions 13. Mmcnob Bit DefinitionsMmcimask Register Mmcimask Mmcprtbuf Register Mmcprtbuf14. Mmcprtbuf Bit Definitions 15. Mmcimask Bit Definitions Sheet 115. Mmcimask Bit Definitions Sheet 2 Mmcireg Register MmciregMmcimask Register MultiMediaCard Controller 4 3 2 116. Mmcireg Bit Definitions CMD Comm Mode Abbreviation Index 18. Command Index Values Sheet 1Mmccmd Register Mmccmd 17. Mmccmd Register18. Command Index Values Sheet 2 Mmcargh Register Mmcargh 18. Command Index Values Sheet 3Mmcargl Register Mmcargl 19. Mmcargh Bit Definitions21. MMCRES, Fifo Entry Mmcres Fifo22. MMCRXFIFO, Fifo Entry Responsedata23. MMCTXFIFO, Fifo Entry MultiMediaCard Controller Register Summary24. MMC Controller Registers Sheet 1 Writedata24. MMC Controller Registers Sheet 2 Network SSP Serial Port FeaturesProcessor and DMA Fifo Access SSP Serial Port I/O SignalsOperation Data Formats Trailing Bytes in the Receive Fifo16-4 Intel PXA255 Processor Developer’s Manual TI Synchronous Serial Protocol* Details SPI Protocol Details Motorola SPI* Frame Protocol multiple transfers Serial Clock Phase SPH16-8 Intel PXA255 Processor Developer’s Manual Microwire* Protocol Details PSP Details Programmable Serial Protocol multiple transfers Sspspscmode Programmable Serial Protocol PSP ParametersSspspsfrmp Sspspstrtdly11. TI SSP with SSCRTTE=1 and SSCRTTELP=0 Hi-Z on SsptxdMotorola SPI Programmable Serial Protocol 16-16 Intel PXA255 Processor Developer’s Manual Baud-Rate Generation Fifo Operation16-18 Intel PXA255 Processor Developer’s Manual SSCR0 SSCR0 Bit Definitions Sheet 1SCR SSE FRF DSSEdss SCR SSE SSCR0 Bit Definitions Sheet 2Data Size Select Edss DSSSclkdir Sfrmdir Scfr Ttelp TTE EbceiSSCR1 SPH SPO LBM TIE RIESSP Programmable Serial Protocol Register Sspsp Sspsp Bit Definitions Sheet 1 SSP Interrupt Test Register Ssitr SSP Time Out Register SstoSspsp Bit Definitions Sheet 2 Ssto Bit DefinitionsTest Transmit Fifo Service Request Ttfs Test Receive Fifo Service Request TrfsSsitr Bit Definitions SsitrSssr Sssr Bit Definitions Sheet 1BCE CSS TUR TintSssr Bit Definitions Sheet 2 Sssr Bit Definitions Sheet 3 Transmit Fifo Service RequestSSP Busy Receive Fifo not Empty10. Nssp Register Address Map Network SSP Serial Port Register SummarySsdr Data TRANSMIT/RECEIVE Data16-30 Intel PXA255 Processor Developer’s Manual Hardware Uart Hardware Uart Operation Uart Signal Descriptions17-4 Intel PXA255 Processor Developer’s Manual Fifo Polled Mode Operation Fifo Interrupt Mode OperationCharacter Timeout Interrupt Receive InterruptFifo DMA Mode Operation DMA Receive Programming ErrorsDMA Error Handling Removing Trailing Bytes In DMA Mode Autoflow ControlAuto-Baud-Rate Detection 17-8 Intel PXA255 Processor Developer’s Manual Intel PXA255 Processor Developer’s Manual 17-9 Transmit Holding Register THR Receive Buffer Register RBRDivisor Latch Registers DLL and DLH Bit Reserved Byte Bits Name Description 318Divisor Latch Register High DLH Bit Definitions Interrupt Enable Register IERDLL DLHPhysical Address Interrupt Enable Register IER 0x41600004 Bit Reset ? ? ? ? ? ? ? Bits Name? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 Description IIR Interrupt Identification Register IIRABL TOD IID NIPInterrupt Identification Register Decode Sheet 1 Priority Type Source Reset Control0x41600008 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 0Fifo Control Register FCR Interrupt Identification Register Decode Sheet 210. FCR Bit Definitions Sheet 1 Receive Fifo Occupancy Register for 10. FCR Bit Definitions Sheet 211. for Bit Definitions Auto-Baud Count Register ACR Auto-Baud Control Register ABR12. ABR Bit Definitions ABT13. ACR Bit Definitions Line Control Register LCR14. LCR Bit Definitions Sheet 1 ACR14. LCR Bit Definitions Sheet 2 Line Status Register LSRLine Control Register LCR PXA255 Processor Hardware Uart Dlab Stkyp EPS PEN STB WLS15. LSR Bit Definitions Sheet 1 0x41600014 Bit? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 Bits 15. LSR Bit Definitions Sheet 2 Modem Control Register MCRLine Status Register LSR PXA255 Processor Hardware Uart 0 0 0 0 Bits Name Description16. MCR Bit Definitions Sheet 1 0x41600010 Bit Reset ? ? ? ? ? ? ? BitsPhysical Address Modem Control Register MCR AFEModem Status Register MSR 16. MCR Bit Definitions Sheet 217. MSR Bit Definitions Sheet 1 Infrared Selection Register ISR Scratchpad Register SCR17. MSR Bit Definitions Sheet 2 18. SCR Bit Definitions19. ISR Bit Definitions Hardware Uart Register Summary20. Hwuart Register Locations Sheet 1 Rxpl Txpl Xmode Rcveir Xmitir20. Hwuart Register Locations Sheet 2 Intel PXA255 Processor Developer’s Manual 17-27