System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 8 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

 

 

48 MHz clock. (output) Peripheral clock output derived

 

 

48MHz/GP[7]

ICOCZ

from the PLL.

Pulled High -

Note [3]

NOTE: This clock is only generated when the USB unit

Note[1]

 

 

 

 

 

clock enable is set.

 

 

 

 

 

 

 

RTCCLK/

ICOCZ

Real time clock. (output) 1 Hz output derived from the

Pulled High -

Note [3]

GP[10]

32kHz or 3.6864MHz output.

Note[1]

 

 

 

 

 

 

 

3.6MHz/GP[11]

ICOCZ

3.6864 MHz clock. (output) Output from 3.6864 MHz

Pulled High -

Note [3]

oscillator.

Note[1]

 

 

 

 

 

 

 

 

32kHz/GP[12]

ICOCZ

32 kHz clock. (output) Output from the 32 kHz oscillator.

Pulled High -

Note [3]

Note[1]

 

 

 

 

 

 

 

 

 

Miscellaneous Pins

 

 

 

BOOT_SEL

IC

Boot select pins. (input) Indicates type of boot device.

Input

Input

[2:0]

 

 

 

 

 

 

 

 

 

 

 

Power Enable for the power supply. (output) When

 

Driven low while

 

 

 

entering sleep

PWR_EN

OC

negated, it signals the power supply to remove power to

Driven High

mode. Driven high

 

 

the core because the system is entering sleep mode.

 

when sleep exit

 

 

 

 

sequence begins.

 

 

 

 

 

 

 

Main Battery Fault. (input) Signals that main battery is

 

 

 

 

low or removed. Assertion causes PXA255 processor to

 

 

nBATT_FAULT

IC

enter sleep mode or force an Imprecise Data Exception,

Input

Input

which cannot be masked. PXA255 processor will not

 

 

 

 

 

 

recognize a walk-up event while this signal is asserted.

 

 

 

 

Minimum assertion time for nBATT_FAULT is 1 ms.

 

 

 

 

 

 

 

 

 

VDD Fault. (input) Signals that the main power source is

 

 

 

 

going out of regulation. nVDD_FAULT causes the

 

 

 

 

PXA255 processor to enter sleep mode or force an

Input

Input

nVDD_FAULT

IC

Imprecise Data Exception, which cannot be masked.

 

 

nVDD_FAULT is ignored after a walk-up event until the

 

 

 

 

power supply timer completes (approximately 10 ms).

 

 

 

 

Minimum assertion time for nVDD_FAULT is 1 ms.

 

 

 

 

 

 

 

 

 

Hard reset. (input) Level sensitive input used to start the

 

Input. Driving low

 

 

processor from a known address. Assertion causes the

 

 

 

 

during sleep will

 

 

current instruction to terminate abnormally and causes a

 

 

 

Input

cause normal

nRESET

IC

reset. When nRESET is driven high, the processor starts

reset sequence

 

 

execution from address 0. nRESET must remain low until

 

 

 

 

and exit from sleep

 

 

the power supply is stable and the internal 3.6864 MHz

 

 

 

 

mode.

 

 

oscillator has stabilized.

 

 

 

 

 

 

 

 

 

 

 

 

Reset Out. (output) Asserted when nRESET is asserted

Driven low during

 

nRESET_OUT

OC

and deasserts after nRESET is deasserted but before the

any reset sequence

Driven Low

first instruction fetch. nRESET_OUT is also asserted for

- driven high prior to

 

 

 

 

 

“soft” reset events: sleep, watchdog reset, or GPIO reset.

first fetch.

 

JTAG and Test Pins

 

 

 

 

 

JTAG Test Interface Reset. Resets the JTAG/Debug

 

 

 

 

port. If JTAG/Debug is used, drive nTRST from low to

 

 

nTRST

IC

high either before or at the same time as nRESET. If

Input

Input

 

 

JTAG is not used, nTRST must be either tied to nRESET

 

 

 

 

or tied low.

 

 

 

 

 

 

 

 

 

JTAG test data input. (input) Data from the JTAG

 

 

TDI

IC

controller is sent to the PXA255 processor using this pin.

Input

Input

 

 

This pin has an internal pull-up resistor.

 

 

 

 

 

 

 

2-16

Intel® PXA255 Processor Developer’s Manual

Page 46
Image 46
Intel manual Pin & Signal Descriptions for the PXA255 Processor Sheet 8, Rtcclk Icocz, Bootsel, Pwren, Tdi