AC’97 Controller Unit

Table 13-16. MCSR Bit Definitions

Physical Address

MCSR Register

AC’97 Controller Unit

4050_0018

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

reserved

4

3

2

1

0

FIFOE

 

reserved

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

Bits

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31:5

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO error (FIFOE)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = No Receive FIFO error has occurred.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 = A receive FIFO error occurred. This bit is set if a receive FIFO overrun occurs. In this

 

 

 

4

 

 

FIFOE

 

 

case, the FIFO pointers don't increment, the incoming data from the AC-link is not

 

 

 

 

 

 

 

 

written into the FIFO and will be lost. This could happen due to DMA controller having

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

excessive bandwidth requirements and hence not being able to flush out the Receive

 

 

 

 

 

 

 

 

 

 

FIFO in time.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit is cleared by writing a 1 to this bit position.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3:0

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13.8.3.11Mic-In Data Register (MCDR)

The Mic-In Data Register is a read-only register. A write to this register has no effect. A read to this register gets a 32-bit sample from the Mic-in Receive FIFO.

This is a read-only register. Ignore reads from reserved bits.

Table 13-17. MCDR Bit Definitions

 

 

 

Physical Address

 

 

 

 

 

MCDR Register

 

 

 

 

 

 

AC’97 Controller Unit

 

 

 

 

 

 

 

4050_0060

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

MIC_IN_DAT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31:16

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15:0

 

MIC_IN_DAT

mic-in data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13-28

Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual Mic-In Data Register Mcdr, Mcsr Bit Definitions, Mcdr Bit Definitions, Micindat