Clocks and Power Manager

2.The PWR_EN signal is asserted and the Power Manager waits for the external power supply to stabilize. If nVDD_FAULT is asserted after the external power supply timer expires, the processor returns to Sleep Mode.

3.If PCFR[OPDE] and OSCC[OON] were set when Sleep Mode started, the 3.6864 MHz oscillator is enabled and stabilizes. Otherwise, the 3.6864 MHz oscillator is already stable and this step is bypassed.

4.The processor’s PLL clock generator is reprogrammed with the values in the CCCR and stabilizes.

5.The Sleep Mode configuration in PWRMODE[M] is cleared.

6.The processor’s internal reset is deasserted and the CPU begins a normal boot sequence. When the normal boot sequence begins, all of the processor’s units, except the RTC and portions of the Clocks and Power Manager and the Memory Controller, return to their predefined reset settings.

7.The nRESET_OUT pin is deasserted. This indicates that the processor is about to perform a fetch from the Reset vector.

8.Clear PSSR[PH] before accessing GPIOs, including chip selects that are muxed with GPIOs.

9.Clear PCFR[FS] and PCFR[FP] if either was set before Sleep Mode was triggered.

10.The SDRAM must transition out of self-refresh mode and into its idle state. See Section 6, “Memory Controller” for details on configuring the SDRAM interface.

11.Software must examine the RCSR, to determine what caused the reboot, and the Power Manager Sleep Status register (PSSR), to determine what triggered Sleep Mode.

12.If the PSPR was used to preserve any critical states during Sleep Mode, software can now recover the information.

If the nVDD_FAULT or nBATT_FAULT pin is asserted during the Sleep Mode exit sequence, the system re-enters Sleep Mode in the following sequence:

1.Regardless of the state of the IDAE bit:

All GPIO edge detects and the RTC alarm interrupt are cleared.

The Power Manager wake-up source registers (PWER, PRER, and PFER) are loaded with 0x0000 0003, their wake-up fault state. This limits the potential wake-up sources to a rising or falling edge on GPIO[0] or GPIO[1]. The wake-up fault state prevents spurious events from causing an unwanted wake-up while the battery is low or the power supply is at risk. The fault state is also the default state after a Hardware Reset.

2.The PLL clock generators are disabled.

3.If the OPDE bit in the PCFR is set and the OON bit in the OSCC is set, the 3.6864 MHz oscillator is disabled. If the oscillator is disabled, Sleep Mode consumes less power. If it is enabled, Sleep Mode exits more quickly.

4.An internal reset is generated to the core and most peripheral modules. This reset asserts the nRESET_OUT pin.

5.The PWR_EN pin is deasserted. If PMFW[FWAKE] is cleared, the system must respond by grounding the VCC and PLL_VCC power supplies to minimize power consumption.

Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual Clocks and Power Manager