I2C Bus Interface Unit

on the acknowledge pulse in receiver mode. After the processor reads the IDBR, the ACK/NAK Control bit is written and the Transfer Byte bit is written, allowing the next byte transfer to proceed to the I2C bus. The IDBR register is 0x00 after reset.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 9-9. IDBR Bit Definitions

 

 

 

Physical Address

 

 

 

I2C Data Buffer Register

 

 

 

 

I2C Bus Interface Unit

 

 

 

 

 

 

 

4030_1688

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

IDB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31:8

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7:0

 

 

IDB

 

I2C Data Buffer: Buffer for I2C bus send/receive data.

 

 

 

 

 

 

 

 

 

 

9.9.3I2C Control Register (ICR)

The processor uses the ICR, shown in Table 9-10, to control the I2C unit.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 9-10. ICR Bit Definitions (Sheet 1 of 3)

 

 

 

Physical Address

 

 

 

 

I2C Control Register

 

 

 

 

4030_1690

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FM

 

UR

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

12

SADIE

 

ALDIE

 

 

 

 

0

0

11

10

SSDIE

 

BEIE

 

 

 

 

0

0

9

IRFIE

0

I2C Bus

8

7

ITEIE

 

GCD

 

 

 

 

0

0

Interface Unit

6

5

4

3

IUE

 

SCLE

 

MA

 

TB

 

 

 

 

 

 

 

 

 

 

0

0

0

0

2

ACKNAK

0

1

0

STOP

 

START

 

0

 

 

 

 

31:16

reserved

15

FM

Fast Mode:

0 = 100 KBit/sec. operation

 

 

1 = 400 KBit/sec. operation

 

 

 

14

UR

Unit Reset:

0 = No reset.

 

 

1 = Reset the I2C unit only.

 

 

Slave Address Detected Interrupt Enable:

13SADIE 0 = Disable interrupt.

1= Enables the I2C unit to interrupt the processor when it detects a slave address match or general call address.

12

ALDIE

Arbitration Loss Detected Interrupt Enable:

0 =

Disable interrupt.

 

 

1 =

Enables the I2C unit to interrupt the processor when it loses arbitration in master mode.

Slave STOP Detected Interrupt Enable:

11SSDIE 0 = Disable interrupt.

1= Enables the I2C unit to interrupt the processor when it detects a STOP condition in slave mode.

Intel® PXA255 Processor Developer’s Manual

9-23

Page 353
Image 353
Intel PXA255 manual 3 I2C Control Register ICR, Idbr Bit Definitions, ICR Bit Definitions Sheet 1