Intel PXA255 manual Lookup Palette, Temporal Modulated Energy Distribution Tmed Dithering

LCD Controller

1, 2, 4, or 8-bits, the FIFO entries are unpacked and used to index the palette RAM to read the color value. In 16-bit passive mode, the entries bypass the palette and go directly to the TMED dither logic. In 16-bit active mode, the pixels are sent directly to the pins.

7.3.2Lookup Palette

The internal palette RAM holds up to 256 16-bit color values. Color palette RAM entries are 16 bits wide, with 5 bits of red, 6 bits of green, and 5 bits of blue. Monochrome entries are 8 bits wide. Encoded pixel values from the input FIFO are used as an address to index and select individual palette locations. 1-bit pixel encodings address the first 2 entries, 2-bit pixel encodings address the first 4 entries, 4-bit pixel encodings address 16 locations, and 8-bit pixel encodings select any of the 256 palette entries. In 16-bit pixel mode, the palette RAM is not used and must not be loaded.

7.3.3Temporal Modulated Energy Distribution (TMED) Dithering

For passive displays, entries selected from the lookup palette (or directly from memory for 16-bit pixels) are sent to the TMED dithering algorithm. TMED is a form of temporal dithering, also know as frame rate control. The algorithm determines whether a pixel is on or off.

Understanding how the TMED dithering algorithm works is not necessary to use the processor LCD controller. However, certain characteristics of the algorithm can be controlled through the use of the TMEDRGB Seed Register (Table 7-14) and the TMED Control Register (TCR, Table 7-15). If these registers are to be modified from their default values, refer to this section. Figure 7-2illustrates the TMED concept.

Figure 7-2. Temporal Dithering Concept - Single Color

	Time		X	Y
	(frame #)		position	position
	8 bits			1 bit	Low	EYE
Color		Temporal			Pass
Code		Modulator			Filter
					(Panel)

This dithering concept is applied separately to each color displayed. Each color has zeros added to make the data for each color 8 bits. If a monochrome display is used, only a single matrix (blue) is used.

The processor LCD Controller implements the following algorithm, which is used by TMED to determine an upper and lower boundary:

LowerBoundary = [(PixelValue * FrameNumber) mod 256] + Offset

UpperBoundary = [(PixelValue + LowerBoundary) mod 256]

A 16x16 matrix uses the row (line), column (pixel number), and frame number (which wraps back to 0 from 255) to select a matrix value. When the matrix value is between the lower and upper boundaries from the algorithm, the LCD controller sends a “1” to the LCD panel. The boundaries created by the algorithm are circular, wrapping from 255 back to 0, as shown in Figure 7-3.

7-6 Intel® PXA255 Processor Developer’s Manual