Intel PXA255 manual Fifo Polled Mode Operation, DMA Requests, Transmit Interrupt

UARTs

After the processor reads one character from the receive FIFO or a new start bit is received, the character timeout indication interrupt is cleared and the timeout is reset. If a character timeout indication interrupt has not occurred, the timeout is reset when a new character is received or the processor reads the receive FIFO.

10.4.3.3Transmit Interrupt

Transmit interrupts can only occur when the transmit FIFO and transmit interrupt are enabled. The transmit data request interrupt occurs when the transmit FIFO is at least half empty. The interrupt is cleared when the THR is written or the IIR is read.

10.4.4FIFO Polled Mode Operation

When the FIFOs are enabled, setting IER[7] and IER[4:0] to all zeroes puts the serial port in the FIFO polled mode of operation. The receiver and the transmitter are controlled separately. Either one or both can be in the polled mode. In polled mode, software checks receiver and transmitter status via the LSR.

10.4.5DMA Requests

The FIFO data is one byte wide. DMA requests are either transmit data service requests or receive data service requests. DMA requests are only generated in FIFO mode.

The transmit DMA request is generated when the transmit FIFO is at least half empty and IER[DMAE] is set. After the transmit DMA request is generated, the DMA Controller (DMAC) writes data to the FIFO. For each DMA request, the DMAC sends 8, 16, or 32 bytes of data to the FIFO. The number of bytes to be transmitted is programmed in the DMA channel.

The receive DMA request is generated when the receive FIFO reaches its trigger level with no errors in its entries and the IER[DMAE] is set. A receive DMA request is not generated if the trigger level is set to 1.

The DMAC then reads data from the FIFO. For each DMA request, the DMA controller can read 8, 16 or 32 bytes of data from the FIFO. The number of bytes to be read is programmed in the DMA channel.

Note: Do not program the channel to read more data than the FIFO trigger level.

If DMA requests are enabled and an erroneous character is received, the receive DMA requests are automatically disabled and an error interrupt is generated. The erroneous character is placed in the receive FIFO. If the UART was requesting a receive DMA transaction, the request is immediately cancelled. This prevents the DMAC from attempting to access the FIFOs while software clears the error.

When all the errors in the receive FIFO are cleared, receive DMA requests are automatically enabled and can be generated when the trigger level is reached.

10-22 Intel® PXA255 Processor Developer’s Manual