Intel PXA255 manual UDC Endpoint x Control/Status Register UDCCS4/9/14, Bits 64 Reserved

USB Device Controller

12.6.6.1Transmit FIFO Service (TFS)

The transmit FIFO service bit is be set if one or fewer data packets remain in the transmit FIFO. UDCCSx[TFS] is cleared when two complete data packets are in the FIFO. A complete packet of data is signified by loading 256 bytes or by setting UDCCSx[TSP].

12.6.6.2Transmit Packet Complete (TPC)

The the UDC sets transmit packet complete bit when an entire packet is sent to the host. When this bit is set, the IRx bit in the appropriate UDC status/interrupt register is set if transmit interrupts are enabled. This bit can be used to validate the other status/error bits in the endpoint(x) control/status register. The UDCCSx[TPC] bit gets cleared by writing a one to it. This clears the interrupt source for the IRx bit in the appropriate UDC status/interrupt register, but the IRx bit must also be cleared.

Setting this bit does not prevent the UDC from transmitting the next buffer. The UDC issues NAK handshakes to all IN tokens if this bit is set and neither buffer has been triggered by writing

64 bytes or setting UDCCSx[TSP].

When DMA is used to load the transmit buffers, the interrupt generated by UDCCSx[TPC] can be masked to allow data to be transmitted without core intervention.

12.6.6.3Flush Tx FIFO (FTF)

The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx FIFO bit is set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or SET_INTERFACE. The bit’s read value is zero.

12.6.6.4Transmit Underrun (TUR)

The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When the UDC experiences an underrun, UDCCSx[TUR] generates an interrupt. UDCCSx[TUR] is cleared by writing a 1 to it.

12.6.6.5Bits 6:4 Reserved

Bits 6:4 are reserved for future use.

12.6.6.6Transmit Short Packet (TSP)

Software uses the transmit short packet to indicate that the last byte of a data transfer has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized packet is ready to transmit. Software must not set this bit if a packet of 256 bytes is to be transmitted. When the data packet is successfully transmitted, this bit is cleared by the UDC.

These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.

12.6.7UDC Endpoint x Control/Status Register (UDCCS4/9/14)

UDCCS4/9/14, shown in Table 12-18, contains six bits that are used to operate endpoint(x), an Isochronous OUT endpoint.

12-32 Intel® PXA255 Processor Developer’s Manual