Intel PXA255 manual LCD Controller

LCD Controller

value that causes the FIFO to wait from 0 to 255 clock cycles after the completion of one DMA request to the start of the next request. When PDD=0x00, the FIFO DMA request delay function is disabled.

LCD Quick Disable Interrupt Mask (QDM) — used to mask interrupt requests that are asserted after the LCD Enable bit (ENB) is cleared and the DMAC finishes the current burst transfer. The LCD controller immediately stops requesting new data and the current frame is not completed. This shutdown is for Sleep shutdown. When QDM=0, the quick disable interrupt is enabled, and whenever the LCD quick disable (QD) status bit in the LCD Status Register (LCSR) is set, an interrupt request is made to the interrupt controller. When QDM=1, the quick disable interrupt is masked and the state of the QD status bit is ignored by the interrupt controller. Setting QDM does not affect the current state of QD or the LCD controller’s ability to set and clear QD, it only blocks the generation of the interrupt request.

LCD Disable (DIS) — During LCD Controller operation, setting DIS=1 causes the LCD Controller to finish fetching the current frame from memory and then shut down cleanly. If the LCD DMAC is loading the palette RAM when DIS is set, the load will complete followed by the next frame, and then the LCD controller is disabled. Completion of the current frame is signalled by the LCD when it sets the LCD disable done flag (LDD) in register LCSR. Use a read-modify- write procedure to set this bit, since the other bit fields within LCCR0 continue to be used until the current frame is completed. The LCD Enable bit (ENB) is cleared when the disable is completed. Section 7.2.2 for more information.

Double-Pixel Data (DPD) Pin Mode — selects whether four or eight data pins are used for pixel data output to the LCD screen in single-panel monochrome mode. When DPD=0, L_DD[3:0] pins are used to send 4 pixel values each pixel clock transition. When DPD=1, L_DD[7:0] pins are used to send 8 pixel values each pixel clock. See Table 7-3for a comparison of how the LCD’s data pins are used in each of its display modes.

Note: DPD does not affect dual-panel monochrome mode, any of the color modes, or active mode. Clear DPD in these modes.

Passive/Active Display Select (PAS) — selects whether the LCD controller operates in passive (STN) or active (TFT) display control mode. When PAS=0, passive mode is selected. All LCD data flow operates normally (including the LCD’s dither logic), and all LCD controller pin timing operates as described in Table 7.5.

When PAS=1, active mode is selected. 1- and 2-bit pixel modes are not supported in active mode. For 4- and 8-bit pixel modes, pixel data is transferred via DMA from off-chip memory to the input FIFO, unpacked, and used to select an entry from the palette, just as in passive mode. However, the value read from the palette bypasses the LCD controller’s dither logic and is sent directly to the output FIFO to be driven onto the LCD’s data pins. This 16-bit output to the pins represents 5 bits of red, 6 bits of green, and 5 bits of blue data. For 16-bit pixel encoding mode, two 16-bit values are packed into each word in the frame buffer. Each 16-bit value is transferred via DMA from off- chip memory to the input FIFO. Unlike 4 and 8 bit per pixel modes, the 16-bit value bypasses both the palette and the dither logic and is placed directly in the output FIFO to be sent to the LCD’s data pins. Using the 16-bit pixel encoding mode allows a total of 64K colors to be generated.

The 16-bit output from either the palette or frame buffer to the pins can be organized in any fashion necessary to correctly interface with the LCD panel. Typically, the output is configured into one of three user-specified RGB color formats: 6 bits of red, 5 bits of green, and 5 bits of blue data; 5 bits of red, 6 bits of green, and 5 bits of blue data; and 5 bits of red, 5 bits of green, and 6 bits of blue data. The RGB format 5:6:5 is normally used, since the human eye can distinguish more shades of green than of red or blue.

Intel® PXA255 Processor Developer’s Manual 7-19