Intel PXA255 manual Sxcnfg Bit Definitions Sheet 2, SXLATCH2, SXRL2 SXCL2 SXEN2, SXLATCH0

Memory Controller
Table 6-13.				SXCNFG Bit Definitions (Sheet 2 of 4)
				0x4800_001C										SXCNFG										Memory Controller
Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

reserved Reset 0

SXLATCH2

0

SXTP2		SXCA2		SXRA2		SXRL2			SXCL2			SXEN2		reserved
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

SXLATCH0

*

SXTP0	SXCA0	SXRA0	SXRL0	SXCL0	SXEN0
* *	* *	* * * * *		* * * 0 *

Bits Name Description

CAS Latency for SX Memory partition pair 2/3

Number of external SDCLK cycles between receiving the READ command and latching the data. The unit size for SXCL2 is the external SDCLK cycle. When SX Memory runs at half the memory clock frequency (MDREFR:K0DB2 = 1), the delay is 2*memclk. When in doubt as to which CAS Latency to use, use the next larger.

		IF SXTP2 = 00”(SMROM):
		000	– reserved
		001	– reserved
		010	– 3 clocks
		011 – 4 clocks
		100	– 5 clocks
20:18	SXCL2	101	– 6 clocks
		110 – reserved
		111 – reserved
		IF SXTP2 = 10 (non-SDRAM timing Fast Flash)
		000 – reserved
		001	– reserved
		010	– 3 clocks
		011 – 4 clocks
		100	– 5 clocks
		101	– 6 clocks
		110 – 7 clocks
		111 – reserved
		Enable Bits for SX Memory Partition 2 (bit 16) and Partition 3 (bit 17)
17:16	SXEN2	0 – Partition is not Enabled as SX Memory
		1 – Partition is Enabled as SX Memory
15	—	reserved
		SXMEM latching scheme for pair 0/1
		0 – Latch return data with fixed delay on MEMCLK
14	SXLATCH0	1 – Latch return data with return clock
		Must always be written with a 1 to enable the return clock SDCLK for latching data. For
		more detail on this return data latching, see Section 6.5.4

SX Memory type for partition pair 0/1

		00	– Synchronous Mask ROM (SMROM)
13:12	SXTP0	01	– reserved
		10	– non-SDRAM-like Synchronous Flash
		11 – reserved

6-34 Intel® PXA255 Processor Developer’s Manual