Intel PXA255 manual Expansion Card Interface Timing Diagrams and Parameters

Contents
		6.2.1	SDRAM Interface Overview	6-2
		6.2.2	Static Memory Interface / Variable Latency I/O Interface	6-3
		6.2.3	16-Bit PC Card / Compact Flash Interface	6-4
	6.3	Memory System Examples		6-4
	6.4	Memory Accesses		6-7
		6.4.1	Reads and Writes	6-8
		6.4.2	Aborts and Nonexistent Memory	6-8
	6.5	Synchronous DRAM Memory Interface		6-8
		6.5.1	SDRAM MDCNFG Register (MDCNFG	6-8
		6.5.2	SDRAM Mode Register Set Configuration Register (MDMRS)	6-12
		6.5.3	SDRAM MDREFR Register (MDREFR)	6-14
		6.5.4	Fixed-Delay or Return-Clock Data Latching	6-17
		6.5.5	SDRAM Memory Options	6-18
		6.5.6	SDRAM Command Overview	6-27
		6.5.7	SDRAM Waveforms	6-28
	6.6	Synchronous Static Memory Interface		6-32
		6.6.1	Synchronous Static Memory Configuration Register (SXCNFG)	6-32
		6.6.2	Synchronous Static Memory Mode Register Set Configuration
			Register (SXMRS)	6-37
		6.6.3	Synchronous Static Memory Timing Diagrams	6-38
		6.6.4	Non-SDRAM Timing SXMEM Operation	6-39
	6.7	Asynchronous Static Memory		6-42
		6.7.1	Static Memory Interface	6-42
		6.7.2	Static Memory SA-1111 Compatibility Configuration Register (SA1111CR)	6-44
		6.7.3	Asynchronous Static Memory Control Registers (MSCx)	6-46
		6.7.4	ROM Interface	6-50
		6.7.5	SRAM Interface Overview	6-53
		6.7.6	Variable Latency I/O (VLIO) Interface Overview	6-55
		6.7.7	FLASH Memory Interface	6-58
	6.8	16-Bit PC Card/Compact Flash Interface		6-60
		6.8.1	Expansion Memory Timing Configuration Register	6-60
		6.8.2	Expansion Memory Configuration Register (MECR)	6-63
		6.8.3	16-Bit PC Card Overview	6-64
		6.8.4	External Logic for 16-Bit PC Card Implementation	6-66
		6.8.5	Expansion Card Interface Timing Diagrams and Parameters	6-69
	6.9	Companion Chip Interface		6-70
		6.9.1	Alternate Bus Master Mode	6-72
	6.10	Options and Settings for Boot Memory		6-74
		6.10.1	Alternate Booting	6-74
		6.10.2	Boot Time Defaults	6-74
		6.10.3	Memory Interface Reset and Initialization	6-78
	6.11	Hardware, Watchdog, or Sleep Reset Operation		6-79
	6.12	GPIO Reset Procedure		6-81
	6.13	Memory Controller Register Summary		6-81
7	LCD Controller		..............................................................................................................................	7-1
	7.1	Overview		7-1
		7.1.1	Features	7-2
		7.1.2	Pin Descriptions	7-4
	7.2	LCD Controller Operation		7-4
vi			Intel® PXA255 Processor Developer’s Manual