Intel PXA255 manual Case 2 EP0 Control Read with a Premature Status Stage

USB Device Controller

14.When the host executes the STATUS OUT stage (zero-length OUT), the UDC sets the UDDCS0[OPR] bit, which causes an interrupt.

15.Software enters the ISR routine and determines that the UDCCS0[OPR] bit is set, the UDCCS0[SA] bit is clear, and its internal state machine is EP0_END_XFER. Software clears the UDCCS0[OPR] bit and transfers its internal state machine to EP0_IDLE.

16.Software clears the UDC interrupt bit and returns from the interrupt service routine.

If the host sends another SETUP command during these steps, the software must terminate the first SETUP command and start the new command.

12.5.2Case 2: EP0 Control Read with a Premature Status Stage

Case 2 occurs during an enumeration cycle when the host PC sends a premature status stage during a Get Device Descriptor command.

1.When software starts, it initializes a software state machine to EP0_IDLE. The software state machine is used to track endpoints stages when software communicates with the host PC.

2.The host PC sends a SETUP command.

3.UDC generates an EP0 Interrupt.

4.Software determines that the UDCCS0[SA] and UDCCS0[OPR] bits are set. This indicates that a new OUT packet is in the EP0 Buffer and identifies a SETUP transaction.

5.Software reads the data into a buffer while UDCCS0[RNE] bit (receiver not empty) is set.

6.Software parses the command in the buffer and determines that it is a Control Read.

7.Software starts to load the UDDR0 register FIFO with the first data packet and sets the internal state machine to EP0_IN_DATA_PHASE.

8.After it reads and parses the data, software clears the UDCCS0[SA] and the UDCCS0[OPR] bits and sets the UDCCS0[IPR] bit, if transmitting less than MAX_PACKET bytes, which prompts the UDC to transmit the data on the next IN. The UDC sends NAKs to all requests on this EP until the UDCCS0[IPR] bit is set.

9.Software clears the UDC interrupt bit and returns from the interrupt service routine.

10.The host PC issues an IN packet, which the UDC sends back to the host. After the host PC sends an ACK to the UDC, the UDC clears the UDDCS0[IPR] bit and generates an interrupt.

11.Software enters the ISR routine and examines its internal state machine. It determines that it is in the EP0_IN_DATA_PHASE state and must transmit more data. Software loads the next amount of data, sets the UDCCS0[IPR] bit, if transmitting less than MAX_PACKET bytes, and returns from the interrupt. The internal state machine is not affected.

12.Repeat Steps 10 and 11 until all the data is transmitted or the last data packet is a short packet.

13.As Steps 10 and 11 are repeated, the host sends a premature STATUS OUT stage, which indicates that the host PC can not accept more data, instead of an IN packet.

14.When the EP0 interrupt occurs, software determines that the UDCCS0[OPR] bit is set, the UDCCS0[SA] bit is cleared, and its machine state is EP0_IN_DATA_PHASE. This indicates that a premature STATUS OUT occurred.

15.Software clears the UDCCS0[OPR] bit and changes the pin’s state to EP0_IDLE. The software writes to the UDCCS0[FTF] bit to clean up any buffer pointers and empty the transmit FIFO.

Intel® PXA255 Processor Developer’s Manual 12-13