I2C Bus Interface Unit

9.4I2C Bus Operation

The I2C unit transfers data in 1-byte increments and always follows this sequence:

1)START

2)7-bit Slave Address

3)R/nW Bit

4)Acknowledge Pulse

5)8 Bits of Data

6)ACK/NAK Pulse

7)Repeat of Steps 5 and 6 for required number of bytes

8)Repeated START (Repeat Step 1) or STOP

9.4.1Serial Clock Line (SCL) Generation

When the I2C unit is in master-transmit or master-receive mode, it generates the I2C clock output. The SCL clock is generated by setting the ICR[FM] bit for either 100KBit/sec or 400Kbit/sec operation.

9.4.2Data and Addressing Management

The I2C Data Buffer Register (IDBR) and the I2C Slave Address Register (ISAR) manage data and slave addressing. The IDBR (see Section 9.9.2) contains one byte of data or a 7-bit slave address and the R/nW bit. The ISAR contains the processor programmable slave address. The I2C unit puts received data in the IDBR after a full byte is received and acknowledged. To transmit data, the CPU writes to the IDBR, and the I2C unit passes the information to the serial bus when the ICR[TB] bit is set. See Section 9.9.3.

When the I2C unit is in master- or slave-transmit mode:

1.Software writes data to the IDBR over the internal bus. This initiates a master transaction or sends the next data byte after the ISR[ITE] bit is set.

2.I2C unit transmits data from the IDBR when the ICR[TB] bit is set.

3.When enabled, an IDBR transmit empty interrupt is signalled when a byte is transferred on the I2C bus and the acknowledge cycle is complete.

4.When the I2C unit is ready to transfer the next byte before the CPU has written the IDBR and a STOP condition is not in place, the I2C unit inserts wait states until the CPU writes a new value into the IDBR and sets the ICR[TB] bit.

When the I2C unit is in master- or slave-receive mode:

1.The processor reads IDBR data over the internal bus after the IDBR receive full interrupt is signalled.

2.I2C unit transfers data from the shift register to the IDBR after the acknowledge cycle completes.

3.I2C unit inserts wait states until the IDBR is read. Refer to Section 9.4.3 for acknowledge pulse information in receiver mode.

4.After the CPU reads the IDBR, the I2C unit writes the ICR[ACKNAK] bit and the ICR[TB] bit, allowing the next byte transfer to proceed.

Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual I2C Bus Operation, Serial Clock Line SCL Generation, Data and Addressing Management