I2C Bus Interface Unit

Table 9-6. Slave Transactions

I2C Slave Action

Mode of

 

Definition

 

Operation

 

 

 

 

I2C unit monitors all slave address transactions.

 

 

ICR[IUE] bit must be set.

 

 

I2C unit monitors bus for START conditions. When a START is

 

 

 

detected, the interface reads the first 8 bits and compares the most

 

 

 

significant seven bits with the 7-bit ISAR and the general call

Slave-receive

Slave-receive

 

address (0x00). If there is a match, the I2C unit sends an ACK.

(default mode)

only

If the first 8 bits are zero’s, this is a general call address. If the

 

 

 

ICR[GCD] bit is clear, both the ISR[GCAD] bit and the ISR[SAD] bit

 

 

 

will be set. See Section 9.4.8.

 

 

If the eighth bit of the first byte (R/nW bit) is low, the I2C unit stays in

 

 

 

slave-receive mode and the ISR[SAD] bit is cleared. If R/nW bit is

 

 

 

high, I2C unit switches to slave-transmit and ISR[SAD] bit is set.

 

 

Indicates the interface has detected an I2C operation that addresses

Setting the Slave

 

 

the processor including the general call address. The processor can

Slave-receive

 

distinguish an ISAR match from a General Call by reading the

Address

 

Slave-transmit

 

ISR[GCAD] bit.

Detected bit

 

An interrupt is signalled, if enabled, after the matching slave address

 

 

 

 

 

 

is received and acknowledged.

 

 

 

 

 

 

Data receive mode of I2C slave operation.

 

 

Eight bits are read from the serial bus into the shift register. When a

 

 

 

full byte is received and the ACK/NAK bit is completed, the byte is

Read one byte of

 

 

transferred from the shift register to the IDBR.

Slave-receive

Occurs when the ISR[IRF] bit is set and the ICR[TB] bit is clear. If

I2C Data from the

IDBR

only

 

enabled, the IDBR Receive Full Interrupt is signalled to the CPU.

 

Software reads one data byte from the IDBR. When the IDBR is

 

 

 

 

 

read, the processor writes the desired ICR[ACKNAK] bit and sets

 

 

 

the ICR[TB] bit. This causes the I2C unit to stop inserting wait states

 

 

 

and let the master transmitter write the next piece of information.

 

 

 

 

Transmit

 

As a slave-receiver, the I2C unit pulls the SDA line low to generate

Acknowledge to

Slave-receive

 

the ACK pulse during the high SCL period.

master-

only

ICR[ACKNAK] bit controls the ACK data the I2C unit drives. See

transmitter

 

 

Section 9.4.3.

 

 

 

 

 

 

Data transmit mode of I2C slave operation.

Write one byte of

Slave-transmit

Occurs when ISR[ITE] bit is set and ICR[TB] bit is clear. If enabled,

I2C data to the

 

the IDBR Transmit Empty Interrupt is signalled to the processor.

IDBR

only

The processor writes a data byte to IDBR and sets ICR[TB] bit to start

 

 

 

 

the transfer.

 

 

 

 

Wait for

Slave-transmit

As a slave-transmitter, the I2C unit releases the SDA line to allow the

Acknowledge

 

master-receiver to pull the line low for the ACK.

from master-

only

 

See Section 9.4.3.

receiver

 

 

 

 

 

 

 

 

Figure 9-11through Figure 9-13are examples of I2C transactions and show the relationships between master and slave devices.

Intel® PXA255 Processor Developer’s Manual

9-15

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Intel PXA255 manual Slave Transactions, 2C Slave Action Mode Definition Operation