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Intel PXA255 Programmable Serial Protocol PSP Parameters, Sspspscmode, Sspspsfrmp, Sspspstrtdly

Models: PXA255

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Network SSP Serial Port

Figure 16-10. Programmable Serial Protocol (single transfers)

SSPSCLK
(when SCMODE = 0)
SSPSCLK
(when SCMODE = 1)
SSPSCLK
(when SCMODE = 2)
SSPSCLK
(when SCMODE = 3)
SSPTXD	Undefined	MSB	LSB	End of Transfer
SSPTXD	Undefined	MSB	LSB	Data State
T1	T2	T3		T4
SSPRXD	Undefined	MSB	LSB	Undefined
SSPSFRM
(when SFRMP = 1)
SSPSFRM	T5	T6
SSPSFRM

(when SFRMP = 0)

				A9522-02
Table 16-2. Programmable Serial Protocol (PSP) Parameters

	Symbol	Definition	Range	Units

			(Drive, Sample, SSPSCLK Idle)
		Serial clock mode	0 - Fall, Rise, Low
	—	Serial clock mode	1 - Rise, Fall, Low	—
	—	(SSPSP[SCMODE])	1 - Rise, Fall, Low	—
		(SSPSP[SCMODE])	2 - Rise, Fall, High
			2 - Rise, Fall, High
			3 - Fall, Rise, High

	—	Serial frame polarity	High or Low	—
	—	(SSPSP[SFRMP])	High or Low	—
		(SSPSP[SFRMP])

	T1	Start delay	0 - 7	Clock period
	T1	(SSPSP[STRTDLY])	0 - 7	Clock period
		(SSPSP[STRTDLY])

	T2	Dummy start	0 - 3	Clock period
	T2	(SSPSP[DMYSTRT])	0 - 3	Clock period
		(SSPSP[DMYSTRT])

	T3	Data size	4 - 32	Clock period
	T3	(SSCR0[EDSS] and SSCR0[DSS])	4 - 32	Clock period
		(SSCR0[EDSS] and SSCR0[DSS])

	T4	Dummy stop (SSPSP[DMYSTOP])	0 - 3	Clock period

	T5	SSPSFRM delay (SSPSP[SFRMDLY]	0 - 88	Half clock period

	T6	SSPSFRM width (SSPSP[SFRMWDTH]	1 - 44	Clock period

		End of transfer data state (SSPSP[ETDS])	Low or [bit 0]	—

Note: The SSPSFRM delay must not extend beyond the end of T4. SSPSFRM Width must be asserted for at least 1 SSPSCLK, and must be deasserted before the end of the T4 cycle (i.e. in terms of time, not bit values, (T5 + T6) <= (T1 + T2 + T3 + T4), 1<= T6 < (T2 + T3 + T4), and (T5 + T6) >= (T1

+1) to ensure that SSPSFRM is asserted for at least 2 edges of the SSPSCLK). While the PSP can be programmed to generate the assertion of SSPSFRM during the middle of the data transfer (after the MSB was sent), the SSP is not able to receive data in frame slave mode (SSCR1[SFRMDIR] is

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Intel® PXA255 Processor Developer’s Manual

Page 554

Image 554

Intel PXA255 manual Programmable Serial Protocol PSP Parameters, Sspspscmode, Sspspsfrmp, Sspspstrtdly, Sspspdmystrt

Contents

Intel PXA255 Processor Intel PXA255 Processor Developer’s Manual Contents Power Manager General Configuration Register Pcfr Contents Expansion Card Interface Timing Diagrams and Parameters DMA 10-1 11-1 12.6 14.3 15.5 Figures BitBurst-of-Eight ROM or Flash Read Timing Diagram MSC0RDF = 10-25 Tables Clocks Manager Register Summary Sxcnfg 10-6 10-8 12-26 15-7 Revision History Date Revision DescriptionXxiv Intel XScale Microarchitecture Features System Integration FeaturesUniversal Serial Bus USB Client Clocks and Power ControllersMemory Controller 6 AC97 Controller DMA Controller DmacLCD Controller Inter-IC Sound I2S ControllerGpio Synchronous Serial Protocol Controller SspcInter-Integrated Circuit I2C Bus Interface Unit UARTsPulse-Width Modulator PWM OS TimersReal-Time Clock RTC Interrupt ControlIntroduction System Architecture OverviewIntel XScale Microarchitecture Implementation Options Coprocessor 7 Register 4 Psfs BitCoprocessor 14 Registers 0-3 Performance Monitoring Coprocessor 14 Register 6 and 7- Clock and Power ManagementCPU Core Fault Register Bit Definitions Coprocessor 15 Register 0 ID Register DefinitionPXA255 Processor ID Values Coprocessor 15 Register 1 P-BitID Bit Definitions ARM ID Jtag IDInterrupts I/O OrderingSemaphores USB ResetUnit Sleep Mode Gpio Reset Watchdog Reset Hard Reset ICPInternal Registers Selecting Peripherals vs. General Purpose I/OPin List Power on Reset and Boot OperationPower Management Processor Pin TypesPin & Signal Descriptions for the PXA255 Processor Sheet 1 Pin Name Type Signal Descriptions Reset State Sleep StatePin & Signal Descriptions for the PXA255 Processor Sheet 2 Pin & Signal Descriptions for the PXA255 Processor Sheet 3 PsktselPin & Signal Descriptions for the PXA255 Processor Sheet 4 Pin & Signal Descriptions for the PXA255 Processor Sheet 5 Pin & Signal Descriptions for the PXA255 Processor Sheet 6 Pin & Signal Descriptions for the PXA255 Processor Sheet 7 Rtcclk Icocz Pin & Signal Descriptions for the PXA255 Processor Sheet 8Bootsel PwrenPin & Signal Descriptions for the PXA255 Processor Sheet 9 Pin Description Notes Sheet 1Memory Map Pin Description Notes Sheet 2Memory Map Part One From 0x80000000 to 0xFFFF Ffff Memory Map Part Two From 0x00000000 to 0x7FFF Ffff System Architecture Register Address Summary Sheet 1 Unit Address Register Symbol Register DescriptionSystem Architecture Register Summary System Architecture Register Address Summary Sheet 2 System Architecture Register Address Summary Sheet 3 System Architecture Register Address Summary Sheet 4 System Architecture Register Address Summary Sheet 5 UnitSystem Architecture Register Address Summary Sheet 6 System Architecture Register Address Summary Sheet 7 Unit AddressSystem Architecture Register Address Summary Sheet 8 System Architecture Register Address Summary Sheet 9 System Architecture Register Address Summary Sheet 10 System Architecture Register Address Summary Sheet 11 System Architecture Register Address Summary Sheet 12 Clocks and Power Manager Clock Manager IntroductionPower Manager Introduction Clock ManagerOST Retains Power in SleepPWM SSP Ficp I2C MMC2 3.6864 MHz Oscillator Core Phase Locked Loop1 32.768 kHz Oscillator Core PLL Output Frequencies for 3.6864 MHz Crystal 4 95.85 MHz Peripheral Phase Locked Loop5 147.46 MHz Peripheral Phase Locked Loop SdramClock Gating Resets and Power ModesHardware Reset Watchdog Reset Invoking Gpio Reset Gpio ResetCompleting a Watchdog Reset Behavior During Gpio ResetCompleting Gpio Reset Run ModeTurbo Mode Entering Turbo ModeExiting Turbo Mode Idle ModeBehavior in Turbo Mode Entering Idle ModeFrequency Change Sequence Behavior in Idle ModeExiting Idle Mode Preparing for a Frequency Change SequenceInvoking the Frequency Change Sequence Behavior During the Frequency Change Sequence8 33-MHz Idle Mode Completing the Frequency Change SequenceEntering 33-MHz Idle Mode Behavior in 33-MHz Idle ModeSleep Mode External Voltage Regulator Requirements Sleep ModeExiting 33-MHz Idle Mode Preparing for Sleep Mode Entering Sleep ModeClocks and Power Manager Behavior in Sleep Mode Exiting Sleep ModeClocks and Power Manager Power Mode Exit Sequence Table Sheet 1 Power Mode SummaryPower Mode Entry Sequence Table IdlePower Mode Exit Sequence Table Sheet 2 Power Manager Registers Power Mode Supply Source Module Turbo RunPmcr Power Manager Control Register PmcrPmcr Bit Definitions IdaePcfr Power Manager General Configuration Register PcfrPcfr Bit Definitions OpdeWertc Power Manager Wake-Up Enable Register PwerPwer Bit Definitions Pwer0x40F00010 Power Manager Rising-Edge Detect Enable Register Prer10. Prer Bit Definitions Prer0x40F00014 Power Manager Falling-Edge Detect Enable Register Pfer11. Pfer Bit Definitions Pfer0x40F00018 Power Manager Gpio Edge Detect Status Register Pedr12. Pedr Bit Definitions PedrPssr Power Manager Sleep Status Register Pssr13. Pssr Bit Definitions Sheet 1 RDH14. Pspr Bit Definitions Power Manager Scratch Pad Register Pspr13. Pssr Bit Definitions Sheet 2 CPU VFSPower Manager Fast Sleep Walk-up Configuration Register Pmfw 15. Pmfw Register Bitmap and Bit DefinitionsPGSR0 16. PGSR0 Bit Definitions17. PGSR1 Bit Definitions SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS018. PGSR2 Bit Definitions Reset Controller Status Register RcsrBit Reset 0x40F00028 PGSR219. Rcsr Bit Definitions Core Clock Configuration Register CccrClocks Manager Registers RcsrBit Reserved 20. Cccr Bit Definitions0x41300000 Multiplier =Clock Enable Register Cken 21. Cken Bit Definitions Sheet 1CKEN8 Description I2S Unit Clock Enable21. Cken Bit Definitions Sheet 2 CKEN522. Oscc Bit Definitions Coprocessor 14 Clock and Power ManagementOscillator Configuration Register Oscc 24. Cclkcfg Bit Definitions Core Clock Configuration Register Cclkcfg23. Coprocessor 14 Clock and Power Management Summary Power Supply Connectivity Power Mode Register PwrmodePower-On-Reset Considerations External Hardware ConsiderationsPower Manager Register Summary Clocks and Power Manager Register SummaryDriving the Crystal Pins from an External Clock Source Clocks Manager Register Locations27. Power Manager Register Summary General-Purpose I/O Gpio OperationGeneral-Purpose I/O Block Diagram Gpio Alternate FunctionsGpio Alternate Functions Sheet 1 Gpio Alternate Functions Sheet 2 Mbgnt ALTFN1OUT Gpio Alternate Functions Sheet 3MMCCS0 ALTFN1OUT Gpio Register Definitions Sheet 1 Gpio Register DefinitionsGpio Alternate Functions Sheet 4 GPLR0 Bit Definitions Gpio Pin-Level Registers GPLR0, GPLR1, GPLR2Gpio Register Definitions Sheet 2 GPLR0GPLR2 Bit Definitions Gpio Pin Direction Registers GPDR0, GPDR1, GPDR2GPLR1 Bit Definitions GPLR1GPDR2 Bit Definitions GPDR0 Bit DefinitionsGPDR1 Bit Definitions GPSR0 GPSR0 Bit Definitions10. GPSR1 Bit Definitions PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS013. GPCR1 Bit Definitions 11. GPSR2 Bit Definitions12. GPCR0 Bit Definitions GPCR2 Bit Definitions GPCR217. GRER2 Bit Definitions 15. GRER0 Bit Definitions16. GRER1 Bit Definitions GFER2 Bit Definitions 18. GFER0 Bit Definitions19. GFER1 Bit Definitions 22. GEDR1 Bit Definitions Gpio Edge Detect Status Register GEDR0, GEDR1, GEDR221. GEDR0 Bit Definitions GEDR2 Bit Definitions GEDR2GAFR0L 24. GAFR0L Bit Definitions25. GAFR0U Bit Definitions AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0GAFR1L 26. GAFR1L Bit Definitions27. GAFR1U Bit Definitions GAFR1UGAFR2L 28. GAFR2L Bit Definitions29. GAFR2U Bit Definitions GAFR2UInterrupt Controller Interrupt Controller OperationInterrupt Controller Block Diagram Interrupt Controller Register Definitions30. Icmr Bit Definitions Interrupt Controller Mask Register IcmrInterrupt Controller Level Register Iclr Icmr32. Iccr Bit Definitions Interrupt Controller Control Register Iccr31. Iclr Bit Definitions 33. Icip Bit Definitions 34. Icfp Bit DefinitionsIcpr Interrupt Controller Pending Register Icpr35. Icpr Bit Definitions Sheet 1 IS9 IS8IS14 IS13 IS12 IS11 IS10 Network SSP Service Request Interrupt Pending35. Icpr Bit Definitions Sheet 2 IS16System Integration Unit 35. Icpr Bit Definitions Sheet 336. List of First-Level Interrupts Sheet 1 Bit Position Source Unit36. List of First-Level Interrupts Sheet 2 Real-Time Clock RTCReal-Time Clock Operation RTC Register Definitions RTC Trim Register Rttr38. Rtar Bit Definitions RTC Alarm Register RtarRttr Bit Definitions 39. Rcnr Bit Definitions RTC Counter Register RcnrRTC Status Register Rtsr Rcnr40. Rtsr Bit Definitions Trim ProcedureOscillator Frequency Calibration Trim Example #2 Measured Value Has a Fractional Component Rttr Value CalculationsTrim Example #1 Measured Value Has No Fractional Component Operating System OS Timer Maximum Error Calculation Versus RTC AccuracyOS Timer Match Register 0-3 OSMRx Watchdog Timer OperationOS Timer Register Definitions 42. Oier Bit Definitions OS Timer Interrupt Enable Register Oier41. OSMRx Bit Definitions OSMR3, OSMR2, OSMR1OS Timer Status Register Ossr OS Timer Watchdog Match Enable Register OwerOS Timer Count Register Oscr 43. Ower Bit DefinitionsPulse Width Modulator Operation 0x40A00014 Bit Reset ? ? ? ? ? ? ? ? BitsPulse Width Modulator Ossr Bit DefinitionsPWMn Block Diagram 1.1 InterdependenciesRegister Descriptions Reset SequencePower Management Requirements PWM Control Registers PWMCTRLn0x40B00000 PWM Duty Cycle Registers PWMDUTYn46. PWMCTRLn Bit Definitions PrescalePWMDUTY0, PWMDUTY1 PWM Period Control Register PWMPERVALn47. PWMDUTYn Bit Definitions Fdcycle Dcycle0x40B00008 Pulse Width Modulator Output Wave Example48. PWMPERVALn Bit Definitions 49. Gpio Register Addresses Sheet 1 System Integration Unit Register SummaryGpio Register Locations Real-Time Clock Register Locations OS Timer Register LocationsInterrupt Controller Register Locations 53. Pulse Width Modulator Register Addresses 52. OS Timer Register Addresses Sheet 2Pulse Width Modulator Register Locations Dmac Block Diagram DMA DescriptionDmac Signal List Signal DescriptionsDREQ10 and PREQ370 Signals Signal Signal Type To/From Definition In/OutDmairq Signal DMA Channel Priority SchemeChannel Priority if all channels are running concurrently Channel PriorityPriority Schemes Examples No-Descriptor Fetch ModeDMA Descriptors DMA Channel PriorityDescriptor Fetch Mode No-Descriptor Fetch Mode Channel StateDMA Controller Channel States Servicing an InterruptRead and Write Order Byte Transfer OrderTrailing Bytes Little Endian TransfersTransferring Data Servicing Internal PeripheralsDcmdincsrcaddr = Dcmdflowsrc = Dcmdflowtrg = Dcmd Quick Reference for DMA ProgrammingDMA Quick Reference for Internal Peripherals Sheet 1 DrcmrUnit Function Fifo Address Width Servicing Companion Chips and External PeripheralsDMA Quick Reference for Internal Peripherals Sheet 2 Burst Size SourceDMA Controller Memory-to-Memory Moves DMA Channel Control/Status Register DCSRx Dmac RegistersDMA Interrupt Register Dint Dint Bit DefinitionsReqpend DCSRx Bit Definitions Sheet 1RUN Stopstate Endintr Startintr BuserrintrReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCSRx Bit Definitions Sheet 2DRCMRx Bit Definitions DMA Request to Channel Map Registers DRCMRxDMA Descriptor Address Registers DDADRx ChlnumDescriptor Address DMA Source Address RegistersDDADRx Bit Definitions StopSource Address DMA Target Address Registers DTADRx10. DSADRx Bit Definitions SrcaddrTarget Address DMA Command Registers DCMDx11. DTADRx Bit Definitions TrgaddrEndian Width 12. DCMDx Bit Definitions Sheet 1Incsrcaddr SizeWidth 12. DCMDx Bit Definitions Sheet 2Endian LengthExample 1. How to set up and start a channel ExamplesStruct longddadr longdsadr longdtadr shortlength shortdcmd DMA Controller Register Summary 13. DMA Controller Register Summary Sheet 113. DMA Controller Register Summary Sheet 2 13. DMA Controller Register Summary Sheet 3 13. DMA Controller Register Summary Sheet 4 13. DMA Controller Register Summary Sheet 5 Memory Controller Functional Description Sdram Interface OverviewStatic Memory Interface / Variable Latency I/O Interface Memory System Examples 3 16-Bit PC Card / Compact Flash InterfaceSdram Memory System Example Static Memory System Example Bus Operation Burst Size Memory AccessesDevice Transactions Words BitsAborts and Nonexistent Memory Synchronous Dram Memory InterfaceReads and Writes Sdram Mdcnfg Register MdcnfgMdcnfg Bit Definitions Sheet 1 Mdcnfg Bit Definitions Sheet 2 DADDR2 Mdcnfg Bit Definitions Sheet 3DNB2 DLATCH2Sdram Mode Register Set Configuration Register Mdmrs Mdmrs Bit Definitions Sheet 1Low-Power Sdram Mode Register Set Configuration Register Mdmrs Bit Definitions Sheet 20X4800 Sdram Mdrefr Register MdrefrMdmrslp Register Bit Definitions MdmrslpAPD K2DB2 K2RUN K1DB2 K1RUN E1PIN K0DB2 K0RUN E0PIN Mdrefr Bit Definitions Sheet 1Mdrefr DRI1 1 1 1 1 1 1 Mdrefr Bit Definitions Sheet 20 1 0 0 1 * * 1 APD Fixed-Delay or Return-Clock Data LatchingMdrefr Bit Definitions Sheet 3 Sample Sdram Memory Size Options Sdram Memory OptionsSdram Addressing Modes Number Chips Partition Size1x12x8x32 ‘0’ 1x12x8x16 1x12x9x32 1x12x9x16 1x12x10x32 # Bits‘0’ MA2410 Col Data2x13x10x16 ‘0’ # Bits External Address pins at Sdram RAS Time Not Valid illegal addressing combinationBA0 MA24 MA23MA20 A10MA24 BA1 BA0A11 A10 Memory Controller Sdram Command Overview A12Sdram Waveforms 11. Sdram Command Encoding12. Sdram Mode Register Opcode Table Sdclk DataSDRAMreadsamebankdiffrow SDRAMwrite SDCLK1 SDCKE1Synchronous Static Memory Configuration Register Sxcnfg Synchronous Static Memory InterfaceSxcnfg 13. Sxcnfg Bit Definitions Sheet 10x4800001C SXLATCH2 SXTP2 SXCA2 SXRA2 SXRL2 SXCL2 SXEN2SXRL2 SXCL2 SXEN2 Sxcnfg Bit Definitions Sheet 2SXLATCH2 SXLATCH013. Sxcnfg Bit Definitions Sheet 3 SXCL0 Smrom Memory OptionsSxcnfg Bit Definitions Sheet 4 SXEN0Smrom Sxmrs Synchronous Static Memory Timing Diagrams16. Sxmrs Bit Definitions SXMRS2Non-SDRAM Timing Sxmem Operation Sdclk Sdcke17. Read Configuration Register Programming Values Memclk SDCLK0 MdrefrNon-SDRAM Timing Flash Read Timing Diagram 12shows the burst-of-eight read timing diagramStatic Memory Interface 4.2 K3 Synchronous StrataFlash ResetAsynchronous Static Memory Sram Data Size MA10 DQM30 19 -Bit Bus Write Access20 -Bit Bus Write Access Data Size MA0 DQM1023. SA-1111 Register Bit Definitions 21 -Bit Byte Address Bits MA10 for Reads Based on DQM3022 -Bit Byte Address Bit MA0 for Reads Based on DQM10 Asynchronous Static Memory Control Registers MSCx MSC1 24. MSC0/1/2 Bit Definitions Sheet 1MSC0 MSC224. MSC0/1/2 Bit Definitions Sheet 2 RRR1/3/5 RDN1/3/5 Reset RDF1/3/5Bits Access Name 24. MSC0/1/2 Bit Definitions Sheet 3 SramNOE ROM InterfaceTiming Memory Clocks MSCxRTx Device NWE NOEROM Timing Diagrams and Parameters ClkmemRDN+1 Sram Timing Diagrams and Parameters Sram Interface Overview20shows the timing for Sram writes Variable Latency I/O Vlio Interface Overview Variable Latency I/O Timing Diagrams and Parameters RDF+1+Waits RRR*2+1RDF+1+Waits Flash Memory Timing Diagrams and Parameters Flash Memory Interface23. Asynchronous 32-Bit Flash Write Timing Diagram 2 Writes CMD Data26. MCMEM0/1 Bit Definitions Expansion Memory Timing Configuration Register16-Bit PC Card/Compact Flash Interface MCMEM0MCATT0 27. MCATT0/1 Bit Definitions28. MCIO0/1 Bit Definitions MCATT129. Card Interface Command Assertion Code Table MCMEMxASST XASSTHOLD XASSTWAIT +Mecr Expansion Memory Configuration Register Mecr30. Mecr Bit Definition CIT NOS3 16-Bit PC Card Overview 26 -Bit PC Card Memory Map33. Attribute Memory Space Write Commands 31. Common Memory Space Write Commands32. Common Memory Space Read Commands 34. Attribute Memory Space Read CommandsExternal Logic for 16-Bit PC Card Implementation 37 -Bit I/O Space Write Commands nIOIS16 =38 -Bit I/O Space Read Commands nIOIS16 = DIR Socket Expansion Card Interface Timing Diagrams and Parameters 29 -Bit PC Card Memory or I/O 16-Bit Half-word Access30 -Bit PC Card I/O 16-Bit Access to 8-Bit Device Companion Chip Interface31. Alternate Bus Master Mode 32. Variable Latency IOAlternate Bus Master Mode NVDDFAULT/nBATTFAULT with Pmcridae Enabled Gpio ResetNVDDFAULT/nBATTFAULT with Pmcridae Disabled Boot Time Defaults Options and Settings for Boot MemoryAlternate Booting Bootdef Read-Only Register BootdefBootdef 40. Bootdef Bitmap41. Valid Boot Configurations Based on Processor Type PKG Type Boot SELBoot-Time Configurations Sxcnfg34. Smrom Boot Time Configurations and Register Defaults Mdrefr 03CA 7FFF Memory Interface Reset and InitializationSmrom Pin Name PXA255 Processor Reset Value Hardware, Watchdog, or Sleep Reset Operation42. Memory Controller Pin Reset Values Memory Controller Memory Controller Register Summary Gpio Reset ProcedurePhysical Address Symbol Register Name 43. Memory Controller Register Summary Sheet 143. Memory Controller Register Summary Sheet 2 LCD Controller Features LCD ControllerLCD Controller Block Diagram Enabling the Controller LCD Controller OperationPin Descriptions Pin DescriptionsDisabling the Controller Resetting the ControllerDetailed Module Descriptions Input FIFOsLookup Palette Temporal Modulated Energy Distribution Tmed DitheringCompare Range for Tmed Output FIFOs LCD Controller Pin UsagePassive Display Timing Pixel Data Pins LDDx6 DMA Active Display TimingLCD External Palette and Frame Buffers External Palette BufferExternal Frame Buffer Palette Buffer FormatBits Per Pixel Data Memory Organization 10 Bits Per Pixel Data Memory Organization Passive Mode Functional Timing FrameBufferSize =12. Passive Mode Start-of-Frame Timing Vsync Hsync LbiasRegister Descriptions Lfclk Vsync Llclk Hsync LbiasLCD Controller Control Register 0 LCCR0 LCD Controller LDD LCD Controller Data Pin Utilization Sheet 1 Single Passive Screen Portion Pins LCD Controller Data Pin Utilization Sheet 2LCCR0 Reset X X X X X X X X X X XLCCR0 Bit Definitions Sheet 1 0x44000000 Bit ReservedQDM DIS DPD LCD Controller Control Register 1 LCCR1LCCR0 Bit Definitions Sheet 2 PAS EFM IUM SFM LDM SDS CMS ENBLCD Controller BLW ELW HSW PPL LCD Controller Control Register 2 LCCR2LCCR1 Bit Definitions BLWLCD Controller BFW EFW VSW LPP LCD Controller Control Register 3 LCCR3LCCR2 Bit Definitions BFWLCD Controller LCD Controller 0x4400000C Bit Reserved Reset X X X X 0 0 0LCCR3 Bit Definitions Sheet 1 DPC BPPFrame Descriptors Reset X X XLCD Controller DMA LCCR3 Bit Definitions Sheet 2FDADRx Bit Definitions LCD DMA Frame Descriptor Address Registers FDADRxLCD DMA Frame Source Address Registers FSADRx FDADR0FIDRx Bit Definitions LCD DMA Frame ID Registers FIDRxFSADRx Bit Definitions LCD DMA Command Registers LDCMDx LDCMD1 10. LDCMDx Bit DefinitionsLDCMD0 PALBint BRA LCD DMA Frame Branch Registers FBRx11. FBRx Bit Definitions 0 0 0 0 X X 0 Bits Name DescriptionLCD Controller Status Register Lcsr LCD Controller X X 0x44000038 Bit Reset X XLcsr Bit Definitions Sheet 1 EOF IUU IUL ABC BER SOF LDD13. Liicr Bit Definitions LCD Controller Interrupt ID Register Liidr12. Lcsr Bit Definitions Sheet 2 Sint BS EOF QD OU IUU IUL ABC BER SOF LDDTBS Tmed RGB Seed Register Trgbr14. Trgbr Bit Definitions TRSTmed Control Register TCR 16. LCD Controller Register Summary Sheet 1 LCD Controller Register Summary15. TCR Bit Definitions 16. LCD Controller Register Summary Sheet 2 LCD Controller External Interface to Codec Signal DescriptionExternal Interface to Synchronous Serial Peripherals Name Direction DescriptionSerial Data Formats for Transfer to/from Peripherals Data FormatsData Transfer SSP Format Details Sspsclk Sspsfrm MSB SPI Format DetailsSspsclk Sspsfrm LSBMicrowire Format Details Sspsclk Sspsfrm Ssptxd SsprxdNational Microwire* Frame Format Parallel Data Formats for Fifo StorageFifo Operation and Data Transfers Using Programmed I/O Data TransfersUsing DMA Data Transfers Baud-Rate GenerationSSP Serial Port Registers SSP Control Register 0 SSCR0SSP Control Register 0 SSCR0 Data Size Select DSSSSCR0 Bit Definitions SCRExternal Clock Select ECS Synchronous Serial Port Enable SSEFrame Format FRF SSCR1 Bit Definitions Sheet 1 SSP Control Register 1 SSCR1Serial Clock Rate SCR Loop Back Mode LBM Receive Fifo Interrupt Enable RIETransmit Fifo Interrupt Enable TIE SSCR1 Bit Definitions Sheet 2Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd Serial Clock Phase SPHSerial Clock Polarity SPO Receive Fifo Interrupt/DMA Threshold RFT Microwire Transmit Data Size MwdsTransmit Fifo Interrupt/DMA Threshold TFT Ssprxd Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm SsptxdSsdr Bit Definitions SSP Data Register SsdrTFT and RFT Values for DMA Servicing SSP Status Register Sssr RFL TFL ROR RFS TFS BSY RNE TNF Transmit Fifo Not Full Flag TNFSssr Bit Definitions RFLReceive Fifo Not Empty Flag RNE Transmit Fifo Service Request Flag TFSReceive Fifo Service Request Flag RFS SSP Busy Flag BSYSSP Controller Register Summary SSP Controller Register SummaryReceive Fifo Level RFL Address Abbreviation Full NameSynchronous Serial Port Controller SDA I2C Signal DescriptionSignal Name Input/Output Description SCLI2C Bus Definitions 2C Device Definition2 I2C Bus Interface Modes Mode DescriptionOperational Blocks Modes of OperationStop Star Start and Stop Bus StatesStart and Stop Bit Definitions ConditionStop Condition Start ConditionNo Start or Stop Condition ACK ACK NAKStart ACK Stop NAKData and Addressing Management I2C Bus OperationSerial Clock Line SCL Generation 3 I2C Acknowledge Addressing a Slave DevicePolling ArbitrationSCL Arbitration SDA ArbitrationArbitration Procedure of Two Masters Master Transactions Sheet 1 2C Master Mode Definition Action OperationMaster Operations Master Transactions Sheet 2 Slave Operations Master-Receiver Read from Slave-Transmitter2C Slave Action Mode Definition Operation Slave TransactionsNAK Stop General Call AddressACK Stop General Call Address Second Byte Definitions Least SecondWrite n Bytes as a Slave Slave Mode Programming ExamplesInitialize Unit Read n Bytes as a SlaveMaster Programming Examples Write 1 Byte as a MasterRead 1 Byte as a Master Write 2 Bytes and Repeated Start Read 1 Byte as a MasterGlitch Suppression Logic Reset ConditionsRead 2 Bytes as a Master Send Stop Using the Abort 2 I2C Data Buffer Register Idbr Register Definitions1 I2C Bus Monitor Register Ibmr Ibmr Bit Definitions10. ICR Bit Definitions Sheet 1 3 I2C Control Register ICRIdbr Bit Definitions 10. ICR Bit Definitions Sheet 2 40301690 Bit ResetDisable interrupt Beie Irfie Iteie GCD IUE10. ICR Bit Definitions Sheet 3 Receive mode4 I2C Status Register ISR 40301698 Bit 11. ISR Bit Definitions Sheet 12C Status Register BED SAD12. Isar Bit Definitions 5 I2C Slave Address Register Isar11. ISR Bit Definitions Sheet 2 BED SAD Gcad IRF ITE ALD SSD IBBI2C Bus Interface Unit Feature List UARTsStandard Uart Bluetooth UartFull Function Uart Compatibility withName Type Description Signal DescriptionsUart Signal Descriptions Sheet 1 RXDLSB MSB Uart Signal Descriptions Sheet 2Uart Operational Description Reset Internal Register DescriptionsUart Register Addresses as Offsets of a Base Register AccessedReceive Buffer Register RBR RBR Bit DefinitionsTHR Bit Definitions Transmit Holding Register THRDivisor Latch Registers DLL and DLH DLH Bit Definitions Interrupt Enable Register IERDLL Bit Definitions Interrupt Identification Register IIR IER Bit DefinitionsPriority Level Interrupt origin Interrupt ConditionsIIR Bit Definitions Sheet 1 FIFOES10IIR Bit Definitions Sheet 2 Interrupt ID Bits Interrupt SET/RESET FunctionFcrresetrf 10. Interrupt Identification Register Decode Sheet 111. FCR Bit Definitions Sheet 1 Fifo Control Register FCR10. Interrupt Identification Register Decode Sheet 2 ITLLine Control Register LCR 11. FCR Bit Definitions Sheet 2Uart Dlab Stkyp EPS PEN STB WLS1 WLS0 12. LCR Bit DefinitionsBase+0x0C Fifoe Line Status Register LSR13. LSR Bit Definitions Sheet 1 Temt13. LSR Bit Definitions Sheet 2 Tdrq13. LSR Bit Definitions Sheet 3 Uart Modem Control Register MCR14. MCR Bit Definitions Sheet 1 Loop OUT2 OUT1 RTS DTRBase+0x10 Modem Control Register Modem Status Register MSR14. MCR Bit Definitions Sheet 2 15. MSR Bit Definitions Scratchpad Register SPR Fifo Interrupt Mode OperationCharacter Timeout Indication Interrupt Receive InterruptTransmit Interrupt Fifo Polled Mode OperationDMA Requests Infrared Selection Register ISR Slow Infrared Asynchronous InterfaceTrailing Bytes in the Receive Fifo Operation 17. ISR Bit DefinitionsIR Transmit and Receive Example 19. Btuart Register Summary Sheet 1 Uart Register Summary18. Ffuart Register Summary Dlab Bit Name Description19. Btuart Register Summary Sheet 2 20. Stuart Register SummaryBtmcr Uart Register Differences21. Flow Control Registers in Btuart and Stuart BtmsrFicp Signal Description Ficp Operation11.2.1 4PPM Modulation PPM Modulation EncodingsControl Field Frame FormatAddress Field Data FieldReceive Operation CRC FieldBaud Rate Generation Transmit Operation Transmit and Receive FIFOs Trailing or Error Bytes in the Receive Fifo Ficp Register DefinitionsFicp Control Register 0 ICCR0 ICCR0 Bit Definitions Sheet 1TUS ICCR0 Bit Definitions Sheet 2TXE LBMFicp Control Register 1 ICCR1 ICCR1 Bit DefinitionsFicp Control Register 2 ICCR2 ICCR2 Bit DefinitionsFicp Data Register Icdr Icrd Bit DefinitionsFRE Ficp Status Register 0 ICSR0ICSR0 Bit Definitions Sheet 1 RFSEIF ICSR0 Bit Definitions Sheet 2TUR Ficp Status Register 1 ICSR1 ICSR1 Bit DefinitionsFicp Register Summary Ficp Register SummaryUSB Device Controller USB OverviewUSB Protocol Device ConfigurationEndpoint Configuration IN/OUTUSB States Signalling LevelsBit Encoding Bus State UDC+/UDC- Pin LevelsField Formats Nrzi Bit Encoding ExampleToken Packet Type IN, OUT, and Setup Token Packet FormatPacket Formats Start of Frame Packet TypeHandshake Packet Type Transaction FormatsData Packet Type Bulk Transaction TypeBulk Transaction Formats Isochronous Transaction TypeControl Transaction Type Isochronous Transaction Formats10. Interrupt Transaction Formats UDC Device RequestsInterrupt Transaction Type Request Name Configuration11. Host Device Request Summary Self-Powered Device UDC Hardware ConnectionWhen GPIOn and GPIOx are Different Pins When GPIOn and GPIOx are the Same PinCase 1 EP0 Control Read Bus-Powered DevicesUDC Operation Case 2 EP0 Control Read with a Premature Status Stage 12-14 Intel PXA255 Processor Developer’s Manual Case 5 EP1 Data Transmit BULK-IN Case 4 EP0 No Data CommandSoftware Enables the DMA Software Enables the EP1 Interrupt Case 6 EP2 Data Receive BULK-OUTSoftware Allows the Megacell to Handle the Transaction Software Enables DMACase 7 EP3 Data Transmit ISOCHRONOUS-IN Case 8 EP4 Data Receive ISOCHRONOUS-OUT Software Enables the EP3 InterruptSoftware Enables the SOF Interrupt Intel PXA255 Processor Developer’s Manual 12-19 Case 10 Reset Interrupt Case 9 EP5 Data Transmit INTERRUPT-INCase 12 Resume Interrupt UDC Register DefinitionsCase 11 Suspend Interrupt 12. Udccr Bit Definitions UDC Enable UDEUDC Control Register Udccr UDC Active UDA Reset Interrupt Request RstirReset Interrupt Mask REM UDC Resume RSMUDC Control Function Register Udccfr ACK Control ModeACK Response Enable 13. UDC Control Function RegisterPacket Ready IPR UDC Endpoint 0 Control/Status Register UDCCS0OUT Packet Ready OPR 14. UDCCS0 Bit DefinitionsSent Stall SST Device Remote Wakeup Feature DrwfFlush Tx Fifo FTF Force Stall FSTUDC Endpoint x Control/Status Register UDCCS1/6/11 Setup Active SATransmit Fifo Service TFS 15. UDCCS1/6/11 Bit DefinitionsBit 6 Reserved Transmit Packet Complete TPCTransmit Underrun TUR 16. UDCCS2/7/12 Bit Definitions UDC Endpoint x Control/Status Register UDCCS2/7/12Transmit Short Packet TSP Receive Packet Complete RPC Receive Fifo Service RFSDMA Enable DME Bit 2 Reserved17. UDCCS3/8/13 Bit Definitions UDC Endpoint x Control/Status Register UDCCS3/8/13Receive Short Packet RSP UDC Endpoint x Control/Status Register UDCCS4/9/14 Bits 64 ReservedReceive Overflow ROF 18. UDCCS4/9/14 Bit Definitions19. UDCCS5/10/15 Bit Definitions Sheet 1 UDC Endpoint x Control/Status Register UDCCS5/10/15Bits 54 Reserved 19. UDCCS5/10/15 Bit Definitions Sheet 2 UDC Interrupt Control Register 0 UICR0 UICR0 Interrupt Mask Endpoint x IMx, Where x is 0 through20. UICR0 Bit Definitions IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM021. UICR1 Bit Definitions Interrupt Mask Endpoint x IMx, where x is 8 throughUDC Interrupt Control Register 1 UICR1 UICR1Endpoint 1 Interrupt Request IR1 UDC Status/Interrupt Register 0 USIR0Endpoint 0 Interrupt Request IR0 22. USIR0 Bit DefinitionsEndpoint 4 Interrupt Request IR4 Endpoint 2 Interrupt Request IR2Endpoint 3 Interrupt Request IR3 Endpoint 5 Interrupt Request IR5Endpoint 9 Interrupt Request IR9 UDC Status/Interrupt Register 1 USIR1Endpoint 8 Interrupt Request IR8 Endpoint 10 Interrupt Request IR10UDC Frame Number High Register Ufnhr UDC Frame Number MSB Fnmsb Isochronous Packet Error Endpoint 4 IPE4Isochronous Packet Error Endpoint 9 IPE9 24. Ufnhr Bit DefinitionsUDC Byte Count Register x UBCR2/4/7/9/12/14 Isochronous Packet Error Endpoint 14 IPE14UDC Frame Number Low Register Ufnlr Start of Frame Interrupt Mask SIM26. UBCR2/4/7/9/12/14 Bit Definitions UDC Endpoint 0 Data Register UDDR0Endpoint x Byte Count BC 27. UDDR0 Bit Definitions UDC Endpoint x Data Register UDDR1/6/11UDC Endpoint x Data Register UDDR2/7/12 28. UDDR1/6/11 Bit Definitions29. UDDR2/7/12 Bit Definitions UDC Endpoint x Data Register UDDR3/8/13UDC Endpoint x Data Register UDDR4/9/14 30. UDDR3/8/13 Bit Definitions31. UDDR4/9/14 Bit Definitions USB Device Controller Register SummaryUDC Endpoint x Data Register UDDR5/10/15 32. UDDR5/10/15 Bit DefinitionsUfnlr 33. USB Device Controller Register Summary Sheet 2Ufnhr 33. USB Device Controller Register Summary Sheet 3 AC’97 Controller Unit External Interface to CODECs Signal Configuration StepsExample AC-link Name Direction Description summarySDATAIN0 SDATAIN1 AC-link Digital Serial Interface ProtocolSupported Data Stream Formats Sheet 1 Channel Slots CommentsSync AC-link Audio Output Frame SdataoutSupported Data Stream Formats Sheet 2 AC-link Audio Output Frame Slot 0 Tag Phase Slot 1 Command Address PortSlot 1 Bit Definitions Slot 2 Command Data PortSlot 3 PCM Playback Left Channel Slot 2 Bit DefinitionsSlot 5 Modem Line Codec AC-link Audio Input Frame SdatainSlot 4 PCM Playback Right Channel Slots 6-11 ReservedSync Bit Description Slot 1 Status Address Port/SLOTREQ bitsInput Slot 1 Bit Definitions Sheet 1 Slot 4 PCM Record Right Channel Slot 2 Status Data PortSlot 3 PCM Record Left Channel Slot 5 Optional Modem Line CodecSlots 7-11 Reserved AC-link Low Power ModePowering Down the AC-link Slot 12 I/O StatusWaking up the AC-link Wake up triggered by the CodecAcunit Operation Cold AC’97 ResetWarm AC’97 Reset Wake Up Triggered by the AcunitInitialization 13-16 Intel PXA255 Processor Developer’s Manual Operational Flow for Accessing Codec Registers Clocks and Sampling FrequenciesFIFOs Transmit Fifo ErrorsReceive Fifo Errors Interrupts RegistersGlobal Control Register GCR GCR Bit Definitions Sheet 1Warmrst Global Status Register GSRGCR Bit Definitions Sheet 2 ColdrstRdcs GSR Bit Definitions Sheet 1Cdone Sdone Secres Prires SCR PCR Mint Point PiintPocr Bit Definitions Sheet 1 PCM-Out Control Register PocrGSR Bit Definitions Sheet 2 10. Picr Bit Definitions PCM-In Control Register PicrPocr Bit Definitions Sheet 2 11. Posr Bit Definitions PCM-Out Status Register PosrPCMIn Status Register Pisr 12. Pisr Bit Definitions13. CAR Bit Definitions Codec Access Register CARPCM Data Register Pcdr 14. Pcdr Bit Definitions15. Mccr Bit Definitions Mic-In Control Register MccrMic-In Status Register Mcsr Mccr Register17. Mcdr Bit Definitions Mic-In Data Register Mcdr16. Mcsr Bit Definitions Micindat18. Mocr Bit Definitions Modem-Out Control Register MocrModem-In Control Register Micr Mocr Register19. Micr Bit Definitions Modem-Out Status Register MosrModem-In Status Register Misr 20. Mosr Bit Definitions22. Modr Bit Definitions Modem Data Register Modr21. Misr Bit Definitions ModemdatAccessing Codec Registers 11. Modem Transmit and Receive OperationAddress for a Primary Secondary Audio Codec Modem Codec 23. Address Mapping for Codec Registers Sheet 1Processor Bit Physical 23. Address Mapping for Codec Registers Sheet 2 13.9 AC’97 Register Summary 24. Register Mapping Summary13-36 Intel PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound I2S Controller GP32/SYSCLK GP29/SDATAINController Operation Disabling and Enabling Audio Replay Disabling and Enabling Audio RecordSerial Audio Clocks and Sampling Frequencies Transmit Fifo ErrorsReceive Fifo Errors Supported Sampling Frequencies Fifo and Memory Format14.5.2 I2S and MSB-Justified Serial Audio Formats Sysclk = Bitclk =I2S Data Formats 16 bits Registers Serial Audio Controller Global Control Register SACR0Special purpose Fifo Read/Write function SACR0 Bit DefinitionsTfth and Rfth Values for DMA Servicing Suggested Tfth and Rfth for DMA servicingFifo Write/Read table Efwr StrfDrpl SACR1 Bit DefinitionsEnlbf DrecRFL Serial Audio Clock Divider Register SadivSASR0 Bit Definitions TFLSaicr Bit Definitions Serial Audio Interrupt Clear Register SaicrSadiv Bit Definitions 10. Saimr Bit Descriptions Serial Audio Interrupt Mask Register SaimrSerial Audio Data Register Sadr 11. Sadr Bit DescriptionsTransmit and Receive Fifo Accesses Through the Sadr 14.8 I2S Controller Register Summary12. Register Memory Map Address Register Description Paddr90 NameMultiMediaCard Controller SPI Data Token Format Command Token FormatMMC Data Token Format Mmcmd MmdatMMC Controller Functional Description CRCIntel PXA255 Processor Developer’s Manual 15-5 MMC Signal Description Signal DescriptionMMC Controller Reset Card Initialization SequenceMMC Mode Error Detection SPI ModeClock Control Receive Data FIFO, Mmcrxfifo Data FIFOsResponse Data Fifo Mmcres Transmit Data FIFO, Mmctxfifo Card Communication Protocol DMA and Program I/OBasic, No Data, Command and Response Sequence Mmcclkrt Mmcspi MmcrestoBlock Data Write Block Data Read Stream Data WriteBusy Sequence Stream Data ReadSPI Functionality Enabling SPI ModeMultiMediaCard Controller Operation Start and Stop ClockSingle Data Block Write No Data Command and Response SequenceErase Single Block Read Multiple Block Write Multiple Block ReadStream Write Stream ReadMMC Controller Registers Mmcstrpcl RegisterMmcstat Bit Definitions Sheet 1 MMCStatus Register MmcstatMmcstrpcl Bit Definitions StrpclMmcclkrt Register Mmcclkrt Mmcstat Bit Definitions Sheet 2Mmcspi Bit Definitions Sheet 1 Mmcspi Register MmcspiMmcclk Bit Definitions Mmccmdat Bit Definitions Sheet 1 Mmccmdat Register MmccmdatMmcspi Bit Definitions Sheet 2 10. Mmcresto Bit Definitions Mmcresto Register MmcrestoMmccmdat Bit Definitions Sheet 2 Readto Mmcrdto Register Mmcrdto11. Mmcrdto Register Specifies the length of time before a data read time-out12. Mmcblklen Bit Definitions Mmcblklen Register MmcblklenMmcnob Register Mmcnob 13. Mmcnob Bit Definitions14. Mmcprtbuf Bit Definitions Mmcprtbuf Register MmcprtbufMmcimask Register Mmcimask 15. Mmcimask Bit Definitions Sheet 1Mmcimask Register MultiMediaCard Controller Mmcireg Register Mmcireg15. Mmcimask Bit Definitions Sheet 2 4 3 2 116. Mmcireg Bit Definitions Mmccmd Register Mmccmd 18. Command Index Values Sheet 1CMD Comm Mode Abbreviation Index 17. Mmccmd Register18. Command Index Values Sheet 2 Mmcargl Register Mmcargl 18. Command Index Values Sheet 3Mmcargh Register Mmcargh 19. Mmcargh Bit Definitions22. MMCRXFIFO, Fifo Entry Mmcres Fifo21. MMCRES, Fifo Entry Responsedata24. MMC Controller Registers Sheet 1 MultiMediaCard Controller Register Summary23. MMCTXFIFO, Fifo Entry Writedata24. MMC Controller Registers Sheet 2 Features Network SSP Serial PortOperation Processor and DMA Fifo AccessSSP Serial Port I/O Signals Trailing Bytes in the Receive Fifo Data Formats16-4 Intel PXA255 Processor Developer’s Manual TI Synchronous Serial Protocol* Details SPI Protocol Details Serial Clock Phase SPH Motorola SPI* Frame Protocol multiple transfers16-8 Intel PXA255 Processor Developer’s Manual Microwire* Protocol Details PSP Details Programmable Serial Protocol multiple transfers Sspspsfrmp Programmable Serial Protocol PSP ParametersSspspscmode SspspstrtdlyHi-Z on Ssptxd 11. TI SSP with SSCRTTE=1 and SSCRTTELP=0Motorola SPI Programmable Serial Protocol 16-16 Intel PXA255 Processor Developer’s Manual Fifo Operation Baud-Rate Generation16-18 Intel PXA255 Processor Developer’s Manual SCR SSE SSCR0 Bit Definitions Sheet 1SSCR0 FRF DSSData Size Select SSCR0 Bit Definitions Sheet 2Edss SCR SSE Edss DSSSSCR1 Ttelp TTE EbceiSclkdir Sfrmdir Scfr SPH SPO LBM TIE RIESSP Programmable Serial Protocol Register Sspsp Sspsp Bit Definitions Sheet 1 Sspsp Bit Definitions Sheet 2 SSP Time Out Register SstoSSP Interrupt Test Register Ssitr Ssto Bit DefinitionsSsitr Bit Definitions Test Receive Fifo Service Request TrfsTest Transmit Fifo Service Request Ttfs SsitrBCE CSS TUR Sssr Bit Definitions Sheet 1Sssr TintSssr Bit Definitions Sheet 2 SSP Busy Transmit Fifo Service RequestSssr Bit Definitions Sheet 3 Receive Fifo not EmptySsdr Network SSP Serial Port Register Summary10. Nssp Register Address Map Data TRANSMIT/RECEIVE Data16-30 Intel PXA255 Processor Developer’s Manual Hardware Uart Hardware Uart Uart Signal Descriptions Operation17-4 Intel PXA255 Processor Developer’s Manual Character Timeout Interrupt Fifo Interrupt Mode OperationFifo Polled Mode Operation Receive InterruptDMA Error Handling Fifo DMA Mode OperationDMA Receive Programming Errors Auto-Baud-Rate Detection Removing Trailing Bytes In DMA ModeAutoflow Control 17-8 Intel PXA255 Processor Developer’s Manual Intel PXA255 Processor Developer’s Manual 17-9 Divisor Latch Registers DLL and DLH Receive Buffer Register RBRTransmit Holding Register THR Bit Reserved Byte Bits Name Description 318DLL Interrupt Enable Register IERDivisor Latch Register High DLH Bit Definitions DLH? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 Description Physical Address Interrupt Enable Register IER0x41600004 Bit Reset ? ? ? ? ? ? ? Bits Name ABL TOD IID Interrupt Identification Register IIRIIR NIP0x41600008 Priority Type Source Reset ControlInterrupt Identification Register Decode Sheet 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 010. FCR Bit Definitions Sheet 1 Fifo Control Register FCRInterrupt Identification Register Decode Sheet 2 11. for Bit Definitions Receive Fifo Occupancy Register for10. FCR Bit Definitions Sheet 2 12. ABR Bit Definitions Auto-Baud Control Register ABRAuto-Baud Count Register ACR ABT14. LCR Bit Definitions Sheet 1 Line Control Register LCR13. ACR Bit Definitions ACRLine Control Register LCR PXA255 Processor Hardware Uart Line Status Register LSR14. LCR Bit Definitions Sheet 2 Dlab Stkyp EPS PEN STB WLS? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 Bits 15. LSR Bit Definitions Sheet 10x41600014 Bit Line Status Register LSR PXA255 Processor Hardware Uart Modem Control Register MCR15. LSR Bit Definitions Sheet 2 0 0 0 0 Bits Name DescriptionPhysical Address Modem Control Register MCR 0x41600010 Bit Reset ? ? ? ? ? ? ? Bits16. MCR Bit Definitions Sheet 1 AFE17. MSR Bit Definitions Sheet 1 Modem Status Register MSR16. MCR Bit Definitions Sheet 2 17. MSR Bit Definitions Sheet 2 Scratchpad Register SCRInfrared Selection Register ISR 18. SCR Bit Definitions20. Hwuart Register Locations Sheet 1 Hardware Uart Register Summary19. ISR Bit Definitions Rxpl Txpl Xmode Rcveir Xmitir20. Hwuart Register Locations Sheet 2 Intel PXA255 Processor Developer’s Manual 17-27

Figure 16-10. Programmable Serial Protocol (single transfers)

Table 16-2. Programmable Serial Protocol (PSP) Parameters

(SSPSP[SCMODE])

(SSPSP[SFRMP])

(SSPSP[STRTDLY])

(SSPSP[DMYSTRT])

Intel® PXA255 Processor Developer’s Manual