Intel PXA255 manual Intel XScale Microarchitecture Implementation Options

System Architecture

Figure 2-1. Block Diagram

RTC

OS Timer

PWM(2)

	Int.
	Controller
	Clocks &
	Power Man.	Bus
	I2S
PurposeI/O		Peripheral
	AC97
	I2C
General	UARTs
	NSSP
	Slow IrDA

Fast IrDA

SSP

USB

Client

MMC

DMA Controller and Bridge

Color or

Grayscale

LCD

Controller

System Bus

Intelfi XScale

Microarchitecture

3.6864 32.768

MHz KHz

Osc Osc

Memory

Controller

Variable
Latency I/O	ASIC
Control

PCMCIA	XCVR	Socket 0
& CF		Socket 1
Control

Dynamic	SDRAM/
	SMROM
Memory
	4 banks
Control
Static	ROM/
	Flash/
Memory
	SRAM
Control
	4 banks

2.2Intel XScale® Microarchitecture Implementation Options

The processor incorporates the Intel XScale® microarchitecture which is described in a separate document. This core contains implementation options which an Application Specific Standard Product (ASSP) may elect to implement or omit. This section describes those options.

Most of these options are specified within the coprocessor register space. The processor does not implement any coprocessor registers beyond those defined in the Intel XScale® microarchitecture. The coprocessor registers which are ASSP specific, as stated in the Intel XScale® Microarchitecture for the Intel® PXA255 Processor User’s Manual, order number 278793, are defined in the following sections.

2.2.1Coprocessor 7 Register 4 - PSFS Bit

Bit 5 of this register is defined as the Power Source Fault Status bit or PSFS bit. This bit is set when either nVDD_FAULT or nBATT_FAULT pins are asserted and the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control Register (PMCR) is set.

This is a read-only register. Ignore reads from reserved bits.

2-2 Intel® PXA255 Processor Developer’s Manual