AC’97 Controller Unit

Table 13-7. GCR Bit Definitions (Sheet 2 of 2)

 

 

 

Physical Address

 

 

 

 

 

GCR Register

 

 

 

 

 

 

AC’97 Controller Unit

 

 

 

 

 

 

 

4050_000C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

CDONE_IE

SDONE_IE

 

 

reserved

 

 

SECRDY_IEN

PRIRDY_IEN

reserved

 

SECRES_IEN

PRIRES_IEN

ACLINK_OFF

WARM_RST

COLD_RST

GIE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

Secondary Resume Interrupt Enable:

5SECRES_IEN 0 = Interrupt is disabled

1= Enables an interrupt to occur when the Secondary CODEC causes a resume event on the AC-link

Primary Resume Interrupt Enable:

4PRIRES_IEN 0 = Interrupt is disabled

1= Enables an interrupt to occur when the Primary CODEC causes a resume event on the AC-link

AC-link Shut Off:

0 = If the AC-link was off, turns it back on, otherwise this bit has no effect.

1 = Causes the ACUNIT to drive SDATA_OUT and SYNC outputs low and turn off input

3ACLINK_OFF buffer enables. The reset output is however maintained high. The AC-link will not be allowed to access any of the FIFOs.

 

 

Setting this bit does not ensure a clean shut down. Software must make sure that all

 

 

transactions are complete before setting this bit.

 

 

 

 

 

AC’97 Warm Reset

 

 

0 = A warm reset is not generated.

 

 

1 = Causes a warm reset to occur on the AC-link. The warm reset will awaken a

2

WARM_RST

suspended CODEC without clearing it’s internal registers.

 

 

If software attempts to perform a warm reset while BITCLK is running, the write will be

 

 

ignored and the bit will not change. This bit is self clearing i.e., it remains set until the reset

 

 

completes and BITCLK is seen on the AC-link after which it clears itself.

 

 

 

 

 

AC'97 Cold Reset

 

 

0 = Causes a cold reset to occur throughout the AC'97 circuitry. All data in the ACUNIT

 

 

and the CODEC will be lost.

1

COLD_RST

1 = A cold reset is not generated.

 

 

Defaults to 0. After reset, the driver must to set this bit to a 1.The value of this bit is retained

 

 

after suspends, hence, if this bit was set to a 1 before a suspend, a cold reset is not

 

 

generated on a resume.

 

 

 

 

 

CODEC GPI Interrupt Enable (GIE)

 

 

This bit controls whether the change in status of any Modem CODEC GPI causes an

0

GIE

interrupt.

0 = If this bit is not set, bit 0 of the Global Status Register is set, but an interrupt is not

 

 

generated.

 

 

1 = If this bit is set, the change in value of a GPI (as indicated by bit 0 of slot 12) causes an

 

 

interrupt and sets bit 0 of the Global Status Register

13.8.3.2Global Status Register (GSR)

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Intel® PXA255 Processor Developer’s Manual

13-21

Page 473
Image 473
Intel PXA255 manual Global Status Register GSR, GCR Bit Definitions Sheet 2, Warmrst, Coldrst, Gie