Silicon Laboratories C8051F342 manuals
Communications > Two-Way Radio
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Silicon Laboratories C8051F342 Specifications
282 pages 2.13 Mb
Full Speed USB Flash MCU Family C8051F340/1/2/3/4/5/6/7 WDT ANALOG PERIPHERALS10-bit 200 ksps ADC 64/32 kB ISP FLASH 4/2 kB RAM POR DEBUG CIRCUITRY FLEXIBLE INTERRUPTS 8051 CPU (48/25 MIPS) DIGITAL I/O PRECISION INTERNAL OSCILLATORS HIGH-SPEED CONTROLLER CORE USB Controller / Transceiver 3 C8051F340/1/2/3/4/5/6/77 C8051F340/1/2/3/4/5/6/728 ADC36 C8051F340/1/4/5 Top View122 E M I F(Optional) 123 E M I F(Optional)124 13.6.1.Internal XRAM Only13.6.2.Split Mode without Bank Select 13.6.3.Split Mode with Bank Select 13.6.4.External Only 125 13.7. Timing126 SFR Definition 13.3. EMI0TC: External Memory Timing Control13.7.1.Non-multiplexed Mode 127 Figure 13.5. Non-multiplexed 16-bit MOVX Timing13.7.1.1.16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111. 13.7.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111. 128 Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing13.7.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = 110. 129 Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing130 Figure 13.8. Multiplexed 16-bit MOVX Timing13.7.2.1.16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011. 13.7.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011. 131 Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing13.7.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = 010. 132 Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing133 Tabl e 13.1. AC Parameters for External Memory Interface135 14. Oscillators147 15. Port Input/Output163 16. Universal Serial Bus Controller (USB0)193 17. SMBusFigure 17.1. SMBus Block Diagram 17.1. Supporting Documents 17.2. SMBus Configuration Figure 17.2. Typical SMBus Configuration 17.3. SMBus Operation 194 Master Device SlaveDevice 2 Device 1 Slave 211 18. UART0219 19. UART1 (C8051F340/1/4/5 Only)Figure 19.1. UART1 Block Diagram 221 19.2. Data FormatOptional N bits; N = 5, 6, 7, or 8N bits; N = 5, 6, 7, or 8 Figure 19.4. UART1 Timing With Extra Bit Figure 19.2. UART1 Timing Without Parity or Extra Bit Figure 19.3. UART1 Timing With Parity 222 19.3. Configuration and OperationFigure 19.5. Typical UART Interconnect Diagram19.3.1.Data Transmission 19.3.2.Data Reception 19.3.3.Multiprocessor Communications Figure 19.6. UART Multi-Processor Mode Interconnect Diagram 223 Master Device SlaveSlave 282 CONTACT INFORMATION
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