Silicon Laboratories C8051F347, C8051F346 Configuring Endpoints1-3, Controlling Endpoints1-3

C8051F340/1/2/3/4/5/6/7

USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count

R		R	R	R	R	R	R	R	Reset Value
-					E0CNT				00000000
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	USB Address:
									0x16
Bit7:	Unused. Read = 0; Write = don’t care.
Bits6–0:	E0CNT: Endpoint 0 Data Count
	This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This
	number is only valid while bit OPRDY is a ‘1’.

16.11. Configuring Endpoints1-3

Endpoints1-3 are configured and controlled through their own sets of the following control/status registers: IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of endpoint control/status registers is mapped into the USB register address space at a time, defined by the contents of the INDEX register (USB Register Definition 16.4).

Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 16.5.1. The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH.

When SPLIT = ‘1’, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available.

When SPLIT = ‘0’, the corresponding endpoint functions as either IN or OUT; the endpoint direction is selected by the DIRSEL bit in register EINCSRH.

16.12. Controlling Endpoints1-3 IN

Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware.

An Endpoint1-3 IN interrupt is generated by any of the following conditions:

1.An IN packet is successfully transferred to the host.

2.Software writes ‘1’ to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty.

3.Hardware generates a STALL condition.

16.12.1.Endpoints1-3 IN Interrupt or Bulk Mode

When the ISO bit (EINCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt Mode. Once an end- point has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_INTERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and generate an interrupt.

184 Rev. 0.5