Silicon Laboratories C8051F340 Timers, Programmable Counter Array PCA0, 23.C2 Interface

C8051F340/1/2/3/4/5/6/7
Figure 20.10. SPI Slave Timing (CKPHA = 0)	240
Figure 20.11. SPI Slave Timing (CKPHA = 1)	240
Table 20.1. SPI Slave Timing Parameters	241
21. Timers
Figure 21.1. T0 Mode 0 Block Diagram	244
Figure 21.2. T0 Mode 2 Block Diagram	245
Figure 21.3. T0 Mode 3 Block Diagram	246
Figure 21.4. Timer 2 16-Bit Mode Block Diagram	251
Figure 21.5. Timer 2 8-Bit Mode Block Diagram	252
Figure 21.6. Timer 2 Capture Mode (T2SPLIT = ‘0’)	253
Figure 21.7. Timer 2 Capture Mode (T2SPLIT = ‘1’)	254
Figure 21.8. Timer 3 16-Bit Mode Block Diagram	257
Figure 21.9. Timer 3 8-Bit Mode Block Diagram	258
Figure 21.10. Timer 3 Capture Mode (T3SPLIT = ‘0’)	259
Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’)	260
22.Programmable Counter Array (PCA0)
Figure 22.1. PCA Block Diagram	263
Table 22.1. PCA Timebase Input Options	264
Figure 22.2. PCA Counter/Timer Block Diagram	264
Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules	265
Figure 22.3. PCA Interrupt Block Diagram	265
Figure 22.4. PCA Capture Mode Diagram	266
Figure 22.5. PCA Software Timer Mode Diagram	267
Figure 22.6. PCA High Speed Output Mode Diagram	268
Figure 22.7. PCA Frequency Output Mode	269
Figure 22.8. PCA 8-Bit PWM Mode Diagram	270
Figure 22.9. PCA 16-Bit PWM Mode	271
Figure 22.10. PCA Module 4 with Watchdog Timer Enabled	272
Table 22.3. Watchdog Timer Timeout Intervals1	273
23.C2 Interface
Figure 23.1. Typical C2 Pin Sharing	281

12 Rev. 0.5