Silicon Laboratories C8051F345, C8051F347, C8051F346, C8051F341, C8051F343 Dboen ISO, Eocl, E0CH

C8051F340/1/2/3/4/5/6/7

USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte

R/W		R/W	R/W	R/W	R	R	R	R	Reset Value
DBOEN		ISO	-	-	-	-	-	-	00000000
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	USB Address:
									0x15
Bit7:	DBOEN: Double-buffer Enable
	0: Double-buffering disabled for the selected OUT endpoint.
	1: Double-buffering enabled for the selected OUT endpoint.
Bit6:	ISO: Isochronous Transfer Enable
	This bit enables/disables isochronous transfers on the current endpoint.
	0: Endpoint configured for bulk/interrupt transfers.
	1: Endpoint configured for isochronous transfers.
Bits5–0:	Unused. Read = 000000b; Write = don’t care.

USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low

R R R R R R R R Reset Value

EOCL

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

00000000

USB Address:

0x16

Bits7–0: EOCL: OUT Endpoint Count Low Byte

EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.

USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High

R		R	R	R	R	R	R	R	Reset Value
-		-	-	-	-	-	E0CH		00000000
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	USB Address:
									0x17
Bits7–2:	Unused. Read = 00000. Write = don’t care.
Bits1–0: EOCH: OUT Endpoint Count High Byte

EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.

190 Rev. 0.5