Silicon Laboratories C8051F340, C8051F347, C8051F346, C8051F341 SFR Definition 15.8. P1 Port1 Latch

C8051F340/1/2/3/4/5/6/7

SFR Definition 15.8. P1: Port1 Latch

R/W		R/W	R/W	R/W	R/W	R/W	R/W		R/W	Reset Value
P1.7		P1.6	P1.5	P1.4	P1.3	P1.2	P1.1		P1.0	11111111
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1		Bit0	SFR Address:
								(bit addressable)		0x90
Bits7–0:	P1.[7:0]
	Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’).

0: Logic Low Output.

1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0).

Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input.

0: P1.n pin is logic low.

1: P1.n pin is logic high.

SFR Definition 15.9. P1MDIN: Port1 Input Mode

R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	Reset Value
								11111111
Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	SFR Address:

0xF2

Bits7–0: Analog Input Configuration Bits for P1.7–P1.0 (respectively).

Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled.

0: Corresponding P1.n pin is configured as an analog input.

1: Corresponding P1.n pin is not configured as an analog input.

SFR Definition 15.10. P1MDOUT: Port1 Output Mode

R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	Reset Value
								00000000
Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	SFR Address:
								0xA5

Bits7–0: Output Configuration Bits for P1.7–P1.0 (respectively): ignored if corresponding bit in regis- ter P1MDIN is logic 0.

0: Corresponding P1.n Output is open-drain.

1: Corresponding P1.n Output is push-pull.

156 Rev. 0.5