C8051F340/1/2/3/4/5/6/7
USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable
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| R/W | R/W | R/W | R/W | R/W | R/W | R/W | Reset Value | ||
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| - | - |
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| SOFE | RSTINTE | RSUINTE | SUSINTE | 00000110 |
| Bit7 |
| Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | USB Address: | ||
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| 0x0B |
| Unused. Read = 0000b; Write = don’t care. |
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| Bit3: | SOFE: Start of Frame Interrupt Enable |
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| 0: SOF interrupt disabled. |
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| 1: SOF interrupt enabled. |
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| Bit2: | RSTINTE: Reset Interrupt Enable |
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| 0: Reset interrupt disabled. |
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| 1: Reset interrupt enabled. |
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| Bit1: | RSUINTE: Resume Interrupt Enable |
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| 0: Resume interrupt disabled. |
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| 1: Resume interrupt enabled. |
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| Bit0: | SUSINTE: Suspend Interrupt Enable |
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| 0: Suspend interrupt disabled. |
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| 1: Suspend interrupt enabled. |
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16.9. The Serial Interface Engine
The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automat- ically generated by the SIE. When transmitting data, the SIE will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received.
The SIE will not interrupt the processor when corrupted/erroneous packets are received.
16.10. Endpoint0
Endpoint0 is managed through the USB register E0CSR (USB Register Definition 16.17). The INDEX reg- ister must be loaded with 0x00 to access the E0CSR register.
An Endpoint0 interrupt is generated when:
1.A data packet (OUT or SETUP) has been received and loaded into the Endpoint0 FIFO. The OPRDY bit (E0CSR.0) is set to ‘1’ by hardware.
2.An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted to the host; INPRDY is reset to ‘0’ by hardware.
3.An IN transaction is completed (this interrupt generated during the status stage of the transac- tion).
4.Hardware sets the STSTL bit (E0CSR.2) after a control transaction ended due to a protocol violation.
5.Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the DATAEND bit (E0CSR.3).
180 | Rev. 0.5 |
