Silicon Laboratories C8051F347, C8051F346 SFR Definition 14.6. Clksel Clock Select, Usbclk Clksl

C8051F340/1/2/3/4/5/6/7

SFR Definition 14.6. CLKSEL: Clock Select

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

-		USBCLK		-		CLKSL
Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0

00000000

SFR Address

			0xA9
Bit 7:	Unused. Read = 0b; Write = don’t care.
Bits6–4: USBCLK2–0: USB Clock Select
	These bits select the clock supplied to USB0. When operating USB0 in full-speed mode, the
	selected clock should be 48 MHz. When operating USB0 in low-speed mode, the selected
	clock should be 6 MHz.
	USBCLK	Selected Clock
	000	4x Clock Multiplier
	001	Internal Oscillator / 2
	010	External Oscillator
	011	External Oscillator / 2
	100	External Oscillator / 3
	101	External Oscillator / 4
	110	RESERVED
	111	RESERVED
Bit3:	Unused. Read = 0b; Write = don’t care.
Bits2–0: CLKSL2–0: System Clock SelectThese bits select the system clock source.
	CLKSL	Selected Clock
	000	Internal Oscillator (as determined by the
		IFCN bits in register OSCICN)
	001	External Oscillator
	010	4x Clock Multiplier / 2
	011*	4x Clock Multiplier*
	100	Low-Frequency Oscillator
	101-111	RESERVED
	*Note: This option is only available on 48 MHz devices

144 Rev. 0.5