Silicon Laboratories C8051F341, C8051F347, C8051F346 SFR Definition 11.2. Rstsrc Reset Source

C8051F340/1/2/3/4/5/6/7

SFR Definition 11.2. RSTSRC: Reset Source

R/W	R	R/W	R/W	R	R/W	R/W	R
USBRSF	FERROR	C0RSEF	SWRSF	WDTRSF	MCDRSF	PORSF	PINRSF
Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0

Reset Value

Variable

SFR Address:

	0xEF
Bit7:	USBRSF: USB Reset Flag
	0: Read: Last reset was not a USB reset; Write: USB resets disabled.
	1: Read: Last reset was a USB reset; Write: USB resets enabled.
Bit6:	FERROR: Flash Error Indicator.
	0: Source of last reset was not a Flash read/write/erase error.
	1: Source of last reset was a Flash read/write/erase error.
Bit5:	C0RSEF: Comparator0 Reset Enable and Flag.
	0: Read: Source of last reset was not Comparator0; Write: Comparator0 is not a reset
	source.
	1: Read: Source of last reset was Comparator0; Write: Comparator0 is a reset source
	(active-low).
Bit4:	SWRSF: Software Reset Force and Flag.
	0: Read: Source of last reset was not a write to the SWRSF bit; Write: No Effect.
	1: Read: Source of last was a write to the SWRSF bit; Write: Forces a system reset.
Bit3:	WDTRSF: Watchdog Timer Reset Flag.
	0: Source of last reset was not a WDT timeout.
	1: Source of last reset was a WDT timeout.
Bit2:	MCDRSF: Missing Clock Detector Flag.
	0: Read: Source of last reset was not a Missing Clock Detector timeout; Write: Missing
	Clock Detector disabled.
	1: Read: Source of last reset was a Missing Clock Detector timeout; Write: Missing Clock
	Detector enabled; triggers a reset if a missing clock condition is detected.
Bit1:	PORSF: Power-On / VDD Monitor Reset Flag.
	This bit is set anytime a power-on reset occurs. Writing this bit selects/deselects the VDD
	monitor as a reset source. Note: writing ‘1’ to this bit before the VDD monitor is enabled
	and stabilized can cause a system reset. See register VDM0CN (SFR Definition 11.1).
	0: Read: Last reset was not a power-on or VDD monitor reset; Write: VDD monitor is not a
	reset source.
	1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate;
	Write: VDD monitor is a reset source.
Bit0:	PINRSF: HW Pin Reset Flag.
	0: Source of last reset was not /RST pin.
	1: Source of last reset was /RST pin.

Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a read), read-modify-write instructions read and modify the source enable only. This applies to bits: USBRSF, C0RSEF, SWRSF, MCDRSF, PORSF.

106 Rev. 0.5