Silicon Laboratories C8051F343 Controlling Endpoints1-3 OUT, Dbien ISO Dirsel Fcdt Split

C8051F340/1/2/3/4/5/6/7

USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte

R/W		R/W	R/W	R	R/W	R/W	R	R	Reset Value
DBIEN		ISO	DIRSEL	-	FCDT	SPLIT	-	-	00000000
Bit7		Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0	USB Address:
									0x12
Bit7:	DBIEN: IN Endpoint Double-buffer Enable.
	0: Double-buffering disabled for the selected IN endpoint.
	1: Double-buffering enabled for the selected IN endpoint.
Bit6:	ISO: Isochronous Transfer Enable.
	This bit enables/disables isochronous transfers on the current endpoint.
	0: Endpoint configured for bulk/interrupt transfers.
	1: Endpoint configured for isochronous transfers.
Bit5:	DIRSEL: Endpoint Direction Select.
	This bit is valid only when the selected FIFO is not split (SPLIT = ‘0’).
	0: Endpoint direction selected as OUT.
	1: Endpoint direction selected as IN.
Bit4:	Unused. Read = ‘0’. Write = don’t care.
Bit3:	FCDT: Force Data Toggle.
	0: Endpoint data toggle switches only when an ACK is received following a data packet
	transmission.
	1: Endpoint data toggle forced to switch after every data packet is transmitted, regardless of
	ACK reception.
Bit2:	SPLIT: FIFO Split Enable.
	When SPLIT = ‘1’, the selected endpoint FIFO is split. The upper half of the selected FIFO is
	used by the IN endpoint; the lower half of the selected FIFO is used by the OUT endpoint.
Bits1–0:	Unused. Read = 00b; Write = don’t care.

16.13. Controlling Endpoints1-3 OUT

Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in register EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware.

An Endpoint1-3 OUT interrupt may be generated by the following:

1.Hardware sets the OPRDY bit (EINCSRL.0) to ‘1’.

2.Hardware generates a STALL condition.

16.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode

When the ISO bit (EOUTCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt mode. Once an endpoint has been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0 SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to ‘1’ and generate an interrupt upon reception of an OUT token and data packet. The number of bytes in the current OUT data packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL reg- isters. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset the OPRDY bit to ‘0’.

Rev. 0.5 187